Inki Hong

According to our database1, Inki Hong authored at least 27 papers between 1996 and 2020.

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Bibliography

2020
Residual Simplified Reference Tissue Model with Covariance Estimation.
Proceedings of the 17th IEEE International Symposium on Biomedical Imaging, 2020

2018
Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2012
Slew-aware buffer insertion for through-silicon-via-based 3D ICs.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2007
A hybrid PET-MRI: An integrated molecular-genetic imaging system with HRRT-PET and 7.0-T MRI.
Int. J. Imaging Syst. Technol., 2007

2005
Behavioral synthesis techniques for intellectual property protection.
ACM Trans. Design Autom. Electr. Syst., 2005

2004
A heterogeneous built-in self-repair approach using system-level synthesis flexibility.
IEEE Trans. Reliab., 2004

On Algorithms for Minimum-Cost Quickest Paths with Multiple Delay-Bounds.
Proceedings of the Computational Science and Its Applications, 2004

On Algorithm for All-Pairs Most Reliable Quickest Paths.
Proceedings of the Computational Science, 2004

2001
Symbolic debugging of embedded hardware and software.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000
Symbolic debugging of globally optimized behavioral specifications.
Proceedings of ASP-DAC 2000, 2000

1999
Power optimization using divide-and-conquer techniques for minimization of the number of operations.
ACM Trans. Design Autom. Electr. Syst., 1999

Power optimization of variable-voltage core-based systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors.
Des. Autom. Embed. Syst., 1999

Throughput optimization of general non-linear computations.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Behavioral Synthesis Techniques for Intellectual Property Protection.
Proceedings of the 36th Conference on Design Automation, 1999

1998
High-level synthesis techniques for functional test pattern execution1.
Integr., 1998

Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors.
Proceedings of the 19th IEEE Real-Time Systems Symposium, 1998

On-line scheduling of hard real-time tasks on variable voltage processor.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Techniques for intellectual property protection of DSP designs.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Heterogeneous BISR-approach using System Level Synthesis Flexibility.
Proceedings of the ASP-DAC '98, 1998

Techniques for Functional Test Pattern Execution.
Proceedings of the ASP-DAC '98, 1998

1997
Improved Large-Step Markov Chain Variants for the Symmetric TSP.
J. Heuristics, 1997

DSP Quant: design, validation, and applications of DSP hard real-time benchmark.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

Minimizing the number of operations in DSP computations.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

Potential-Driven Statistical Ordering of Transformations.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Throughput Optimization in Disk-Based Real-Time Application Specific Systems.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Power optimization in disk-based real-time application specific systems.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996


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