Injun Choi
Orcid: 0000-0001-8645-4537
According to our database1,
Injun Choi
authored at least 50 papers
between 1989 and 2024.
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Bibliography
2024
Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024
A Wide-Dynamic-Range, DC-Coupled, Time-Based Neural-Recording IC With Optimized CCO Frequency.
IEEE Access, 2024
Interactive Network Perturbation between Teacher and Students for Semi-Supervised Semantic Segmentation.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024
A Δ-Based Spike Sorting SoC with End-to-End Implementation of Event-Driven Binary Autoencoder Neural Network in Analog CIM Achieving 94.54% Accuracy and 3.11μW/ch.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
An Intra-Body-Power-Transfer System Energized by an Electromagnetic Energy Harvester for Powering Wearable Sensor Nodes.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024
2023
A Process-Scalable Ultra-Low-Voltage Sleep Timer With a Time-Domain Amplifier and a Switch-Less Resistance Multiplier.
IEEE J. Solid State Circuits, October, 2023
A Wide-Bandwidth Ultrasound Receiver and On-Chip Ultrasound Transmitter for Ultrasound Capsule Endoscopy.
IEEE J. Solid State Circuits, October, 2023
Learning Covariance-Based Multi-Scale Representation of Neuroimaging Measures for Alzheimer Classification.
Proceedings of the 20th IEEE International Symposium on Biomedical Imaging, 2023
A 0.9V 2MHz 6.4x-Slope-Boosted Quadrature-Phase Relaxation Oscillator with 164.2dBc/Hz FoM and 62.5ppm Period Jitter in 0.18μm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 333TOPS/W Logic-Compatible Multi-Level Embedded Flash Compute-In-Memory Macro with Dual-Slope Computation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A Wide-Dynamic-Range Neural-Recording IC With Automatic-Gain-Controlled AFE and CT Dynamic-Zoom ΔΣ ADC for Saturation-Free Closed-Loop Neural Interfaces.
IEEE J. Solid State Circuits, 2022
An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
ProST-re: Simulation-Based Analytics for Finding Appropriate Substitutes and Task Reallocation.
IEEE Access, 2022
How Much to Aggregate: Learning Adaptive Node-Wise Scales on Graphs for Brain Networks.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2022, 2022
A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 99.5dB-DR 5kHz-BW Closed-Loop Neural-Recording IC based on Continuous-Time Dynamic-Zoom ΔΣ ADC with Automatic AFE-Gain Control.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A Power-Efficient Radiation Sensor Interface with a Peak-Triggered Sampling Scheme for Mobile Dosimeters.
Sensors, 2020
Comprehensive Simulation and Redesign System for Business Process and Organizational Structure.
IEEE Access, 2020
2019
A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface.
IEEE J. Solid State Circuits, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2015
Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
2014
Incorporating the Effects of Organizational Structure into Business Process Simulation.
Proceedings of the Asia Pacific Business Process Management, 2014
2011
Expert Syst. Appl., 2011
2008
Propagation of engineering changes to multiple product data views using history of product structure changes.
Int. J. Comput. Integr. Manuf., 2008
Terminability and compensatibility of cycles in business processes with a process-oriented trigger.
Data Knowl. Eng., 2008
2007
An integration architecture for knowledge management systems and business process management systems.
Comput. Ind., 2007
2006
Development process and data management of TurnSTEP: a STEP-compliant CNC system for turning.
Int. J. Comput. Integr. Manuf., 2006
Comput. Aided Des., 2006
2005
2004
2003
Comput. Ind., 2003
2002
Int. J. Comput. Integr. Manuf., 2002
Eur. J. Oper. Res., 2002
2000
Int. J. Comput. Integr. Manuf., 2000
1995
On Resolving Schematic Heterogeneity in Multidatabase Systems.
Proceedings of the Modern Database Systems: The Object Model, 1995
1994
Inf. Syst. Res., 1994
1993
Distributed Parallel Databases, 1993
1991
Graph interpretation of methods: a unifying framework for polymorphism in object-oriented programming.
OOPS Messenger, 1991
Formal Specifications And Command Modeling In Software Systems With A Complex Command Structure.
Proceedings of the 12th International Conference on Information Systems, 1991
1990
Object-Oriented Modelling and Reasoning.
Proceedings of the 9th International Conference on Entity-Relationship Approach (ER'90), 1990
Type Restrictions and Method Interfaces in Object-Oriented Database Programming.
Proceedings of the Object-Oriented Databases: Analysis, 1990
1989
Proceedings of the Fifth International Conference on Data Engineering, 1989