Injoon Hong
According to our database1,
Injoon Hong
authored at least 36 papers
between 2012 and 2017.
Collaborative distances:
Collaborative distances:
Timeline
2012
2013
2014
2015
2016
2017
0
5
10
1
4
2
2
1
1
1
3
8
6
4
3
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2017
An Energy-Efficient Speech-Extraction Processor for Robust User Speech Recognition in Mobile Head-Mounted Display Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
An ultra-low-power and mixed-mode event-driven face detection SoC for always-on mobile applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
A 0.5 V 54 µW Ultra-Low-Power Object Matching Processor for Micro Air Vehicle Navigation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
An Energy-Efficient Embedded Deep Neural Network Processor for High Speed Visual Attention in Mobile Vision Recognition SoC.
IEEE J. Solid State Circuits, 2016
A 2.71 nJ/Pixel Gaze-Activated Object Recognition System for Low-Power Mobile Smart Glasses.
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
An 8.3mW 1.6Msamples/s multi-modal event-driven speech enhancement processor for robust speech recognition in smart glasses.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications.
IEEE J. Solid State Circuits, 2015
A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor.
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
A 0.5-degree error 10mW CMOS image sensor-based gaze estimation processor with logarithmic processing.
Proceedings of the Symposium on VLSI Circuits, 2015
18.3 A 0.5V 54μW ultra-low-power recognition processor with 93.5% accuracy geometric vocabulary tree and 47.5% database compression.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
18.1 A 2.71nJ/pixel 3D-stacked gaze-activated object-recognition system for low-power mobile HMD applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 3.13nJ/sample energy-efficient speech extraction processor for robust speech recognition in mobile head-mounted display systems.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Intelligent task scheduler with high throughput NoC for real-time mobile object recognition SoC.
Proceedings of the ESSCIRC Conference 2015, 2015
A keypoint-level parallel pipelined object recognition processor with gaze activation image sensor for mobile smart glasses system.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015
A 1.9nJ/pixel embedded deep neural network processor for high speed visual attention in a mobile vision recognition SoC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
Intelligent Network-on-Chip With Online Reinforcement Learning for Portable HD Object Recognition Processor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Micro, 2014
10.4 A 1.22TOPS and 1.52mW/MHz augmented reality multi-core processor with neural network NoC for HMD applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
An 1.92mW Feature Reuse Engine based on inter-frame similarity for low-power object recognition in video frames.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
An 1.61mW mixed-signal column processor for BRISK feature extraction in CMOS image sensor.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams.
IEEE J. Solid State Circuits, 2013
A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A multi-modal and tunable Radial-Basis-Funtion circuit with supply and temperature compensation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013
2012
IEEE Micro, 2012
A 320mW 342GOPS real-time moving object recognition processor for HD 720p video streams.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A simultaneous multithreading heterogeneous object recognition processor with machine learning based dynamic resource management.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012