Ing-Jer Huang
Orcid: 0000-0003-0206-1010
According to our database1,
Ing-Jer Huang
authored at least 65 papers
between 1992 and 2023.
Collaborative distances:
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Bibliography
2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
2022
Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022
2021
Creating a Scoring System with an Armband Wearable Device for Table Tennis Forehand Loop Training: Combined Use of the Principal Component Analysis and Artificial Neural Network.
Sensors, 2021
2019
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
2016
Full system verification of compatible microprocessors with a dual physical core verification platform.
Proceedings of the International SoC Design Conference, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Proceedings of the VLSI Design, Automation and Test, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Reconfigurable Bus Monitor Tool Suite for on-chip SoC for performance and protocol monitoring.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC.
IEEE Trans. Very Large Scale Integr. Syst., 2011
A Trace-Capable Instruction Cache for Cost-Efficient Real-Time Program Trace Compression in SoC.
IEEE Trans. Computers, 2011
J. Inf. Sci. Eng., 2011
Internet-based hardware/software co-design framework for embedded 3D graphics applications.
EURASIP J. Adv. Signal Process., 2011
2010
A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization.
IEEE Trans. Very Large Scale Integr. Syst., 2010
HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms.
IEICE Trans. Inf. Syst., 2010
An embedded debugging/performance monitoring engine for a tile-based 3D graphics SoC development.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
A Reverse-encoding-based On-chip AHB Bus Tracer Supporting both Post-T and Pre-T Trace.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
A trace-capable instruction cache for cost efficient real-time program trace compression in SoC.
Proceedings of the 46th Design Automation Conference, 2009
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Des. Test Comput., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
NCPA: A Scheduling Algorithm for Multi-cipher and Multi-mode Reconfigurable Cryptosystem.
Proceedings of the 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2008), 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer.
Proceedings of the 45th Design Automation Conference, 2008
Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Proceedings of the 3rd International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007), 2007
SystemC-Based Design Space Exploration of a 3D Graphics Acceleration SoC for Consumer Electronics.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007
Proceedings of the 44th Design Automation Conference, 2007
An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration.
Proceedings of the 44th Design Automation Conference, 2007
An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2003
J. Inf. Sci. Eng., 2003
J. Inf. Sci. Eng., 2003
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
2002
Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Design Exploration of an Industrial Embedded Microcontroller: Performance, Cost and Software Compatibility.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
IEEE Des. Test Comput., 2002
2001
Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors.
ACM Trans. Design Autom. Electr. Syst., 2001
2000
A Machine State Transition Approach to Instruction Retargeting for Embedded Microprocessors.
Des. Autom. Embed. Syst., 2000
Proceedings of ASP-DAC 2000, 2000
1999
J. Inf. Sci. Eng., 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
A Case Study: Synthesis and Exploration of Instruction Set Design for Application-Specific Symbolic Computing.
J. Inf. Sci. Eng., 1998
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation.
Proceedings of the 11th International Symposium on System Synthesis, 1998
Analysis of ×86 instruction set usage for DOS/Windows applications and its implication on superscalar design.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
1992
Proceedings of the 29th Design Automation Conference, 1992
Proceedings of the 29th Design Automation Conference, 1992