Ing-Chao Lin

According to our database, Ing-Chao Lin authored at least 52 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

A Hardware Friendly Variation-Tolerant Framework for RRAM-Based Neuromorphic Computing.

Fang-Yi Gu, Cheng-Han Yang, Ing-Chao Lin, Da-Wei Chang, Darsen D. Lu, Ulf Schlichtmann

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

AttentionRC: A Novel Approach to Improve Locality Sensitive Hashing Attention on Dual-Addressing Memory.

Chun-Lin Chu, Yun-Chih Chen, Wei Cheng, Ing-Chao Lin, Yuan-Hao Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems.

Yu-Guang Chen, Chieh-Shih Wang, Ing-Chao Lin, Zheng-Wei Chen, Ulf Schlichtmann

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

Basis Sharing: Cross-Layer Parameter Sharing for Large Language Model Compression.

Jingcun Wang, Yu-Guang Chen, Ing-Chao Lin, Bing Li, Grace Li Zhang

CoRR, 2024

BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks.

Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Ulf Schlichtmann, Bing Li

CoRR, 2024

GNN-Based INC and IVC Co-Optimization for Aging Mitigation.

Yu-Guang Chen, Hsiu-Yi Yang, Ing-Chao Lin

Proceedings of the IEEE European Test Symposium, 2024

Class-Aware Pruning for Efficient Neural Networks.

Mengnan Jiang, Jingcun Wang, Amro Eldebiky, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Grace Li Zhang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials.

Hoang-Hiep Le, Md. Aftab Baig, Wei-Chen Hong, Cheng-Hsien Tsai, Cheng-Jui Yeh, Fu-Xiang Liang, I-Ting Huang, Wei-Tzu Tsai, Ting-Yin Cheng, Sourav De, Nan-Yow Chen, Wen-Jay Lee, Ing-Chao Lin, Da-Wei Chang, Darsen D. Lu

CoRR, 2023

A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing.

Wei-Lun Chen, Fang-Yi Gu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022

An Efficient Implementation of Convolutional Neural Network With CLIP-Q Quantization on FPGA.

Wei Cheng, Ing-Chao Lin, Yun-Yang Shih

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Low-Power and High-Accuracy Approximate Multiplier With Reconfigurable Truncation.

Fang-Yi Gu, Ing-Chao Lin, Jia-Wei Lin

IEEE Access, 2022

An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine.

Yu-Guang Chen, Chi-Hsu Wang, Ing-Chao Lin

Proceedings of the 19th International SoC Design Conference, 2022

GraphRC: Accelerating Graph Processing on Dual-Addressing Memory with Vertex Merging.

Wei Cheng, Chun-Feng Wu, Yuan-Hao Chang, Ing-Chao Lin

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

WRAP: Weight RemApping and Processing in RRAM-based Neural Network Accelerators Considering Thermal Effect.

Po-Yuan Chen, Fang-Yi Gu, Yu-Hong Huang, Ing-Chao Lin

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network.

Ing-Chao Lin, Chi-Huan Tang, Chi-Ting Ni, Xing Hu, Yu-Tong Shen, Pei-Yin Chen, Yuan Xie

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Rescuing RRAM-Based Computing From Static and Dynamic Faults.

Jilan Lin, Cheng-Da Wen, Xing Hu, Tianqi Tang, Ing-Chao Lin, Yu Wang, Yuan Xie

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

An efficient <i>NBTI</i>-aware wake-up strategy: Concept, design, and manipulation.

Yu-Guang Chen, Ing-Chao Lin, Kun-Wei Chiu, Cheng-Hsuan Liu

Integr., 2021

Exploring Adversarial Examples for Efficient Active Learning in Machine Learning Classifiers.

Honggang Yu, Shihfeng Zeng, Teng Zhang, Ing-Chao Lin, Yier Jin

CoRR, 2021

A Novel NBTI-Aware Chip Remaining Lifetime Prediction Framework Using Machine Learning.

Yu-Guang Chen, Ing-Chao Lin, Yong-Che Wei

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020

A Novel Comparison-Free 1-D Median Filter.

Ing-Chao Lin, Wei-Ting Chen, Yu-Cheng Chou, Pei-Yin Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Global Clean Page First Replacement and Index-Aware Multistream Prefetcher in Hybrid Memory Architecture.

Ing-Chao Lin, Da-Wei Chang, Wei-Jun Chen, Jian-Ting Ke, Po-Han Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems.

Yu-Guang Chen, Yu-Yi Lin, Ing-Chao Lin

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Overview of 2020 CAD Contest at ICCAD.

Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

Infection-Based Dead Page Prediction in Hybrid Memory Architecture.

Ing-Chao Lin, Da-Wei Chang, Chen-Tai Kao, Sheng-Xuan Lin

IEEE Trans. Very Large Scale Integr. Syst., 2019

OCMAS: Online Page Clustering for Multibank Scratchpad Memory.

Da-Wei Chang, Ing-Chao Lin, Yi-Chiao Lin, Wen-Zhi Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration.

Jing-Yuan Luo, Hsiang-Yun Cheng, Ing-Chao Lin, Da-Wei Chang

IEEE Trans. Computers, 2019

Overview of 2019 CAD Contest at ICCAD.

Ulf Schlichtmann, Sabya Das, Ing-Chao Lin, Mark Po-Hung Lin

Proceedings of the International Conference on Computer-Aided Design, 2019

ROAD: Improving Reliability of Multi-core System via Asymmetric Aging.

Yu-Guang Chen, Ing-Chao Lin, Jian-Ting Ke

Proceedings of the International Conference on Computer-Aided Design, 2019

2018

Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes.

Ing-Chao Lin, Yun Kae Law, Yuan Xie

IEEE Trans. Very Large Scale Integr. Syst., 2018

An efficient NBTI-aware wake-up strategy for power-gated designs.

Kun-Wei Chiu, Yu-Guang Chen, Ing-Chao Lin

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

ROHOM: Requirement-Aware Online Hybrid On-Chip Memory Management for Multicore Systems.

Da-Wei Chang, Ing-Chao Lin, Lin-Chun Yong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Reducing aging on scratchpad memory using temporal- and FSM-based power management.

Yun Kae Law, Ing-Chao Lin, Cheng-Chien Lin

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016

Reducing Aging Effects on Ternary CAM.

Ing-Chao Lin, Yen-Han Lee, Sheng-Wei Wang

IEICE Trans. Electron., 2016

2015

High-Performance Low-Power Carry Speculative Addition With Variable Latency.

Ing-Chao Lin, Yi-Ming Yang, Cheng-Chian Lin

IEEE Trans. Very Large Scale Integr. Syst., 2015

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic.

Ing-Chao Lin, Yu-Hung Cho, Yi-Ming Yang

IEEE Trans. Very Large Scale Integr. Syst., 2015

High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies.

Ing-Chao Lin, Jeng-Nian Chiou

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

NBTI and Leakage Reduction Using ILP-Based Approach.

Ing-Chao Lin, Kuan-Hui Li, Chia-Hao Lin, Kai-Chiang Wu

IEEE Trans. Very Large Scale Integr. Syst., 2014

BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs.

Kai-Chiang Wu, Ing-Chao Lin, Yao-Te Wang, Shuen-Shiang Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing.

Yi-Hua Li, Wei-Cheng Lien, Ing-Chao Lin, Kuen-Jong Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management.

Da-Wei Chang, Ing-Chao Lin, Yu-Shiang Chien, Ching-Lun Lin, Alvin W. Y. Su, Chung-Ping Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

NBTI tolerance and leakage reduction using gate sizing.

Ing-Chao Lin, Shun-Ming Syu, Tsung-Yi Ho

ACM J. Emerg. Technol. Comput. Syst., 2014

Analyzing the BTI Effect on Multi-bit Retention Registers.

Ing-Chao Lin, Yao-Te Wang, Shuen-Shiang Yang, Yi-Luen Wu

Proceedings of the Intelligent Systems and Applications, 2014

2013

Leakage and Aging Optimization Using Transmission Gate-Based Technique.

Ing-Chao Lin, Chin-Hung Lin, Kuan-Hui Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Impacts of NBTI and PBTI effects on ternary CAM.

Yen-Han Lee, Ing-Chao Lin, Sheng-Wei Wang

Proceedings of the International Symposium on Quality Electronic Design, 2013

High accuracy approximate multiplier with error correction.

Chia-Hao Lin, Ing-Chao Lin

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy.

Shun-Ming Syu, Yu-Hui Shao, Ing-Chao Lin

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Aging-aware reliable multiplier design.

Yu-Hung Cho, Ing-Chao Lin, Yi-Ming Yang

Proceedings of the IEEE 25th International SOC Conference, 2012

2011

TG-based technique for NBTI degradation and leakage optimization.

Chin-Hung Lin, Ing-Chao Lin, Kuan-Hui Li

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect.

Shi-Qun Zheng, Ing-Chao Lin, Yen-Han Lee

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2006

Transaction Level Error Susceptibility Model for Bus Based SoC Architectures.

Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems.

Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin

Des. Autom. Embed. Syst., 2005

A power estimation methodology for systemC transaction level models.

Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005