Indrani Paul

According to our database1, Indrani Paul authored at least 24 papers between 2002 and 2023.

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Bibliography

2023

AMD Ryzen<sup>™</sup> 7040 Series: Technology Overview.
Proceedings of the 35th IEEE Hot Chips Symposium, 2023

2018
Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques.
CoRR, 2018

2017
Ti-States: Power Management in Active Timing Margin Processors.
IEEE Micro, 2017


Dynamic GPGPU Power Management Using Adaptive Model Predictive Control.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
A framework for evaluating promising power efficiency techniques in future GPUs for HPC.
Proceedings of the 24th High Performance Computing Symposium, 2016

Ti-states: Processor power management in the temperature inversion region.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Measuring and modeling on-chip interconnect power on real hardware.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Performance Boosting Opportunities under Communication Imbalance in Power-Constrained HPC Clusters.
Proceedings of the 45th International Conference on Parallel Processing, 2016

VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency.
Proceedings of the 53rd Annual Design Automation Conference, 2016

A Case for Criticality Models in Exascale Systems.
Proceedings of the 2016 IEEE International Conference on Cluster Computing, 2016

2015
Achieving Exascale Capabilities through Heterogeneous Computing.
IEEE Micro, 2015

Harmonia: balancing compute and memory power in high-performance GPUs.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

A Taxonomy of GPGPU Performance Scaling.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
Coordinated energy management in heterogeneous processors.
Sci. Program., 2014

A comparison of core power gating strategies implemented in modern hardware.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

2013
Cooperative boosting: needy versus greedy power management.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Performance boosting under reliability and power constraints.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
Performance impact of virtual machine placement in a datacenter.
Proceedings of the 31st IEEE International Performance Computing and Communications Conference, 2012

2002
Efficient Implementation of Packet Scheduling Algorithm on High-Speed Programmable Network Processors.
Proceedings of the Management of Multimedia on the Internet, 2002

Algorithms for Switch-Scheduling in the Multimedia Router for LANs.
Proceedings of the High Performance Computing, 2002


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