Indrajit Chakrabarti
Orcid: 0000-0003-4744-2132
According to our database1,
Indrajit Chakrabarti
authored at least 87 papers
between 2008 and 2024.
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Bibliography
2024
Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel.
IEEE Trans. Very Large Scale Integr. Syst., July, 2024
Practical and Efficient PUF-Based Protocol for Authentication and Key Agreement in IoT.
IEEE Embed. Syst. Lett., June, 2024
2023
Low complexity VLSI architecture for improved primal-dual support vector machine learning core.
Microprocess. Microsystems, April, 2023
Theoretical Enumeration of Deployable Single-Output Strong PUF Instances Based on Uniformity and Uniqueness Constraints.
Proceedings of the Information Systems Security - 19th International Conference, 2023
2022
Neuromorph. Comput. Eng., December, 2022
Efficient HEVC Encoding to Meet Bitrate and PSNR Requirements Using Parametric Modeling.
Circuits Syst. Signal Process., 2022
Auditory Model based Phase-Aware Bayesian Spectral Amplitude Estimator for Single-Channel Speech Enhancement.
CoRR, 2022
Systematic realization of a fully connected deep and convolutional neural network architecture on a field programmable gate array.
Comput. Electr. Eng., 2022
2021
A fast integrated deblocking filter and sample-adaptive-offset parameter estimation architecture for HEVC.
Microprocess. Microsystems, September, 2021
Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
ACM J. Emerg. Technol. Comput. Syst., 2021
High speed VLSI architecture for improved region based active contour segmentation technique.
Integr., 2021
IET Circuits Devices Syst., 2021
2020
Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst. Video Technol., 2020
IEEE Trans. Consumer Electron., 2020
Framework for Automated Earthquake Event Detection Based on Denoising by Adaptive Filter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Hexagon Based Compressed Diamond Algorithm for motion estimation and its dedicated VLSI system for HD videos.
Expert Syst. Appl., 2020
2019
A Novel Algorithmic Approach for Efficient Realization of 2-D-DCT Architecture for HEVC.
IEEE Trans. Consumer Electron., 2019
Intelligent Wireless Sensor Nodes for Human Footstep Sound Classification for Security Application.
CoRR, 2019
CoRR, 2019
Time-frequency masking based supervised speech enhancement framework using fuzzy deep belief network.
Appl. Soft Comput., 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Exploring Formaldehyde Sensing Capability of Noble Metal Decorated Reduced Graphene Oxide through First Principle Approach.
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
VLSI architecture for fixed mesh based deformable motion estimation using ARPS algorithm.
Microprocess. Microsystems, 2018
J. Parallel Distributed Comput., 2018
Fast adaptive motion estimation algorithm and its efficient VLSI system for high definition videos.
Expert Syst. Appl., 2018
A High-Speed VLSI Architecture for Motion Estimation Using Modified Adaptive Rood Pattern Search Algorithm.
Circuits Syst. Signal Process., 2018
Power efficient Spiking Neural Network Classifier based on memristive crossbar network for spike sorting application.
CoRR, 2018
Classification of Hand Movements by Surface Myoelectric Signal Using Artificial-Spiking Neural Network Model.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018
2017
Another Look in the Analysis of Cooperative Spectrum Sensing over Nakagami-m Fading Channels.
IEEE Trans. Wirel. Commun., 2017
Signal Process. Image Commun., 2017
Circuits Syst. Signal Process., 2017
Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of (512×512) Frames.
Circuits Syst. Signal Process., 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Improving the Performance of Deep Learning Based Speech Enhancement System Using Fuzzy Restricted Boltzmann Machine.
Proceedings of the Pattern Recognition and Machine Intelligence, 2017
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Deep Recurrent Neural Network Based Monaural Speech Separation Using Recurrent Temporal Restricted Boltzmann Machines.
Proceedings of the 18th Annual Conference of the International Speech Communication Association, 2017
Real-time digitized neural-spike storage scheme in multiple channels for biomedical applications.
Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017
2016
Modelling of Cooperative Spectrum Sensing over Rayleigh Fading Without CSI in Cognitive Radio Networks.
Wirel. Pers. Commun., 2016
Efficient VLSI design of adaptive rood pattern search algorithm for motion estimation of high definition videos.
Microprocess. Microsystems, 2016
J. Circuits Syst. Comput., 2016
Improved single channel phase-aware speech enhancement technique for low signal-to-noise ratio signal.
IET Signal Process., 2016
Very large scale integration architecture for block-matching motion estimation using adaptive rood pattern search algorithm.
IET Circuits Devices Syst., 2016
Circuits Syst. Signal Process., 2016
CoRR, 2016
Global soft decision based speech enhancement using voiced-unvoiced uncertainty and harmonic phase decomposition technique.
Proceedings of the 2016 International Conference on Signal Processing and Communications (SPCOM), 2016
Proceedings of the 17th Annual Conference of the International Speech Communication Association, 2016
Hardware implementation of MIL-STD-1553 protocol over OFDMA-PHY based wireless high data rate avionics systems.
Proceedings of the 2016 IEEE International Conference on Advanced Networks and Telecommunications Systems, 2016
2015
Studies in Computational Intelligence 590, Springer, ISBN: 978-3-319-14376-7, 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip.
Microprocess. Microsystems, 2015
Efficient architecture of adaptive rood pattern search technique for fast motion estimation.
Microprocess. Microsystems, 2015
High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter.
IET Circuits Devices Syst., 2015
Circuits Syst. Signal Process., 2015
CoRR, 2015
Proceedings of the 2015 Fifth National Conference on Computer Vision, 2015
Complexity assisted consistent quality rate control for high resolution H.264 video conferencing.
Proceedings of the 2015 Fifth National Conference on Computer Vision, 2015
Proceedings of the Twenty First National Conference on Communications, 2015
ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
A phase-aware single channel speech enhancement technique using separate bayesian estimators for voiced and unvoiced regions with digital hearing aid application.
Proceedings of the 17th International Conference on E-health Networking, 2015
2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the Twentieth National Conference on Communications, 2014
2013
High performance VLSI implementation of Context-based Adaptive Variable Length Coding (CAVLC) for H.264 encoder.
Proceedings of the Fourth National Conference on Computer Vision, 2013
Proceedings of the Fourth National Conference on Computer Vision, 2013
Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
2012
High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver.
IET Commun., 2012
2011
Power efficient motion estimation algorithm and architecture based on pixel truncation.
IEEE Trans. Consumer Electron., 2011
A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation.
Int. J. Reconfigurable Comput., 2011
2010
IEEE Trans. Consumer Electron., 2010
Low power VLSI architectures for one bit transformation based fast motion estimation.
IEEE Trans. Consumer Electron., 2010
Multi-standard programmable baseband modulator for next generation wireless communication
CoRR, 2010
Proceedings of the Cellular Automata, 2010
2009
IEEE Trans. Consumer Electron., 2009
2008
Proceedings of the Sixth Indian Conference on Computer Vision, Graphics & Image Processing, 2008
Proceedings of the Sixth Indian Conference on Computer Vision, Graphics & Image Processing, 2008
Proceedings of the Cellular Automata, 2008