Indira Nair

According to our database, Indira Nair authored at least 20 papers between 1986 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of two.

2024

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.

Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2020

Pragmatism and Care in Engineering Ethics.

Indira Nair, William M. Bulleit

Sci. Eng. Ethics, 2020

2013

IBM Blue Gene/Q memory subsystem with speculative execution and transactional memory.

Martin Ohmacht, Amy Wang, Thomas Gooding, Ben J. Nathanson, Indira Nair, Geert Janssen, Marcel Schaal, Burkhard D. Steinmacher-Burow

IBM J. Res. Dev., 2013

2012

Power management of multi-core chips: Challenges and pitfalls.

Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta Sharma Gupta, Michael B. Healy, Hans M. Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2010

The Effect of Dynamic Power Management on Mid-Frequency and Low-Frequency Power Supply Noise.

Howard Chen, Indira Nair, Benjamin Mashak

J. Low Power Electron., 2010

Power-efficient, reliable microprocessor architectures: modeling and design methods.

Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Power Management and Its Impact on Power Supply Noise.

Howard Chen, Indira Nair

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008

Exploring power management in multi-core systems.

Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Performance modeling for early analysis of multi-core systems.

Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2005

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems.

Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin

Des. Autom. Embed. Syst., 2005

2004

An efficient system-on-a-chip design methodology for networking applications.

Valentina Salapura, Christos J. Georgiou, Indira Nair

Proceedings of the 2004 International Conference on Compilers, 2004

2003

SEAS: a system for early analysis of SoCs.

Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002

Early analysis tools for system-on-a-chip design.

John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin

IBM J. Res. Dev., 2002

1997

Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system.

Reinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan

IEEE Trans. Very Large Scale Integr. Syst., 1997

1995

AVPGEN-A test generator for architecture verification.

Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal

IEEE Trans. Very Large Scale Integr. Syst., 1995

1994

Architectural Verification of Processors Using Symbolic Instruction Graphs.

Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1992

A Small Test Generator for Large Designs.

Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

Symbolic implication in test generation.

Sandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar

Proceedings of the conference on European design automation, 1991

1986

Evaluating an information system for policy modeling and uncertainty analysis.

Max Henrion, M. Granger Morgan, Indira Nair, Charles Wiecha

J. Am. Soc. Inf. Sci., 1986

Efficient Fault Simulation of CMOS Circuits with Accurate Models.

Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman

Proceedings of the Proceedings International Test Conference 1986, 1986