In-Chul Hwang

Orcid: 0000-0002-0045-9984

According to our database1, In-Chul Hwang authored at least 25 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
A 65-nm duty-cycle corrector achieving 10% to 90% duty-correction range with 0.86% duty-cycle error.
Microelectron. J., 2024

Fast Electrical Balance Duplexer Tuning Using Neural Networks for RF Self-Interference Cancellation in In-Band Full-Duplex Systems.
IEEE Access, 2024

A 40MHz Skewed Crystal Oscillator with Duty Cycle Corrector and Frequency Doubler for WIFI 6 in a 22nm CMOS.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023
A 2.4/5 GHz Dual-Band Low-Noise and Highly Linear Receiver With a New Power-Efficient Feedforward OPAMP for WiFi-6 Applications.
IEEE Access, 2023

2021
Capacitor-Less Dual-Mode All-Digital LDO With ΔΣ-Modulation-Based Ripple Reduction.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges.
IEEE Access, 2021

Tomato Farm Environment Forecasting System Using Machine Learning.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021

2020
Architectural Advancement of Digital Low-Dropout Regulators.
IEEE Access, 2020

A 0.012mm<sup>2</sup>, 0.96-mW All-Digital Multiplying Delay-Locked Loop Based Frequency Synthesizer for GPS-L4 band.
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

2019
Capacitorless Self-Clocked All-Digital Low-Dropout Regulator.
IEEE J. Solid State Circuits, 2019

2016
All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
A 110-nm CMOS 0.7-V Input Transient-Enhanced Digital Low-Dropout Regulator With 99.98% Current Efficiency at 80-mA Load.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
An 180 nm CMOS 1.84-to-3.62 GHz fractional-N frequency synthesizer with skewed-reset PFD for removing noise-folding effect.
IEICE Electron. Express, 2014

2013
Multi-band wide tuning range CMOS VCO with Hybrid Inductor for LTE standard.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2006
Home-based Cooperative Cache for parallel I/O applications.
Future Gener. Comput. Syst., 2006

2005
Design and Implementation of Cooperative Cluster File System.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

2-Phase Protocol: Enhancing Write Performance in Cooperative Cache for PVFS.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

Design and Implementation of the Home-Based Cooperative Cache for PVFS.
Proceedings of the Computational Science, 2005

Fast AFC technique using a code estimation and binary search algorithm for wideband frequency synthesis.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004
A Σ-Δ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications.
IEEE J. Solid State Circuits, 2004

A CMOS self-regulating VCO with low supply sensitivity.
IEEE J. Solid State Circuits, 2004

Design and Implementation of the Cooperative Cache for PVFS.
Proceedings of the Computational Science, 2004

2003
A Σ-Δ fractional-N frequency synthesizer using a wideband integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications.
Proceedings of the ESSCIRC 2003, 2003

2002
A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator.
IEEE J. Solid State Circuits, 2002

2001
A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition.
IEEE J. Solid State Circuits, 2001


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