Imtiaz P. Shaik

According to our database1, Imtiaz P. Shaik authored at least 5 papers between 1995 and 1999.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

1999
A comparison of bridging fault simulation methods.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Testability Features of the AMD-K6 Microprocessor.
IEEE Des. Test Comput., 1998

1997
Testability Features of AMD-K6<sup>TM</sup> Microprocessor.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1995
Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming .
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

A graph approach to DFT hardware placement for robust delay fault BIST.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995


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