Ilya Tuzov

According to our database, Ilya Tuzov authored at least 15 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors.

Jens Anders, Pablo Andreu, Bernd Becker, Steffen Becker, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernández, Nele Mentens, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Matthias Sauer, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner, Nusa Zidaric

Proceedings of the IEEE European Test Symposium, 2023

BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes.

Ilya Tuzov, David de Andrés, Juan-Carlos Ruiz-Garcia, Carles Hernández

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Reversing FPGA architectures for speeding up fault injection: does it pay?

Ilya Tuzov, David de Andrés, Juan Carlos Ruiz

Proceedings of the 18th European Dependable Computing Conference, 2022

Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs.

Ali Asghar, Amanda Katherine Robillard, Ilya Tuzov, Andreas Becher, Daniel Ziener

Proceedings of the Architecture of Computing Systems - 35th International Conference, 2022

2021

Improving the Robustness of Redundant Execution with Register File Randomization.

Ilya Tuzov, Pablo Andreu, Laura Medina, Tomás Picornell, Antonio Robles, Pedro López, José Flich, Carles Hernández

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020

Improving Robustness-Aware Design Space Exploration for FPGA-Based Systems.

Ilya Tuzov, David de Andrés, Juan Carlos Ruiz

Proceedings of the 16th European Dependable Computing Conference, 2020

2019

Simulating the effects of logic faults in implementation-level VITAL-compliant models.

Ilya Tuzov, David de Andrés, Juan Carlos Ruiz

Computing, 2019

Robustness-Aware Design Space Exploration Through Iterative Refinement of D-Optimal Designs.

Ilya Tuzov, David de Andrés, Juan Carlos Ruiz

Proceedings of the 15th European Dependable Computing Conference, 2019

2018

Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study.

Ilya Tuzov, David de Andrés, Juan Carlos Ruiz

J. Parallel Distributed Comput., 2018

Speeding-Up Robustness Assessment of HDL Models through Profiling and Multi-Level Fault Injection.

Ilya Tuzov, David de Andrés, Juan Carlos Ruiz

Proceedings of the 8th Latin-American Symposium on Dependable Computing, 2018

Accurate Robustness Assessment of HDL Models Through Iterative Statistical Fault Injection.

Ilya Tuzov, David de Andrés, Juan Carlos Ruiz

Proceedings of the 14th European Dependable Computing Conference, 2018

DAVOS: EDA Toolkit for Dependability Assessment, Verification, Optimisation and Selection of Hardware Models.

Ilya Tuzov, David de Andrés, Juan Carlos Ruiz

Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2018

2017

Accurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level.

Ilya Tuzov, Juan Carlos Ruiz, David de Andrés

Proceedings of the 13th European Dependable Computing Conference, 2017

Dependability-Aware Design Space Exploration for Optimal Synthesis Parameters Tuning.

Ilya Tuzov, David de Andrés, Juan Carlos Ruiz

Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2017

2016

Speeding-Up Simulation-Based Fault Injection of Complex HDL Models.

Ilya Tuzov, Juan Carlos Ruiz, David de Andrés, Pedro J. Gil

Proceedings of the 2016 Seventh Latin-American Symposium on Dependable Computing, 2016