Igor Loi

Antonio Pullini

Thomas Christoph Müller

IEEE Des. Test, 2017

2016

PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2016

On-the-fly adaptivity for process networks over shared-memory platforms.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.

[BibT_eX]

[DOI]

Frank Kagan Gürkaynak

Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA.

[BibT_eX]

[DOI]

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015

A Modular Shared L2 Memory Design for 3-D Integration.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

PULP: A parallel ultra low power platform for next generation IoT applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

High performance AXI-4.0 based interconnect for extensible smart memory cubes.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014

Energy-efficient vision on the PULP platform for ultra-low power parallel computing.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Online process transformation for polyhedral process networks in shared-memory MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014

A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters.

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013

Exploration and Optimization of 3-D Integrated DRAM Subsystems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects.

[BibT_eX]

[DOI]

Erfan Azarkhish

IET Comput. Digit. Tech., 2013

3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters.

[BibT_eX]

[DOI]

Erfan Azarkhish

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

A shared-FPU architecture for ultra-low power MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, 2013

A high-performance multiported L2 memory IP for scalable three-dimensional integration.

[BibT_eX]

[DOI]

Erfan Azarkhish

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Configurable Low-Latency Interconnect for Multi-core Clusters.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

An energy efficient DRAM subsystem for 3D integrated SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A resilient architecture for low latency communication in shared-L1 processor clusters.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Design space exploration for 3D-stacked DRAMs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

3D NoCs - Unifying inter & intra chip communication.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A new physical routing approach for robust bundled signaling on NoC links.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

An efficient distributed memory interface for many-core platform with 3D stacked DRAM.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Synthesis of low-overhead configurable source routing tables for network interfaces.

[BibT_eX]

[DOI]

Federico Angiolini

Proceedings of the Design, Automation and Test in Europe, 2009

2008

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Developing Mesochronous Synchronizers to Enable 3D NoCs.

[BibT_eX]

[DOI]

Federico Angiolini

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Area and Power Modeling for Networks-on-Chip with Layout Awareness.

[BibT_eX]

[DOI]

VLSI Design, 2007

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow.

[BibT_eX]

[DOI]

Federico Angiolini