Igor Lemberski

According to our database, Igor Lemberski authored at least 16 papers between 1998 and 2021.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of five.

2021

Resubstitution method for big size Boolean logic design targeting look-up-table implementation.

Igor Lemberski, Artjoms Suponenkovs

Int. J. Circuit Theory Appl., 2021

2019

LUT-Oriented Asynchronous Logic Design Based on Resubstitution.

Igor Lemberski, Artjoms Suponenkovs, Marina Uhanova

Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

2018

Asynchronous logiс one-level LUT design based on partial acknowledgement.

Igor Lemberski, Artjoms Suponenkovs

Microelectron. J., 2018

Asynchronous logic design targeting LUTs.

Igor Lemberski, Artjoms Suponenkovs

Proceedings of the 7th Mediterranean Conference on Embedded Computing, 2018

2017

Asynchronous Logic Implementation Based on Factorized DIMS.

Igor Lemberski

J. Circuits Syst. Comput., 2017

2015

Literal Decomposition for LUT-Oriented Asynchronous Dual-Rail Logic Synthesis.

Igor Lemberski

J. Circuits Syst. Comput., 2015

2014

Dual-rail asynchronous logic multi-level implementation.

Igor Lemberski, Petr Fiser

Integr., 2014

Asynchronous sum-of-products logic minimization and orthogonalization.

Igor Lemberski, Petr Fiser, Ruslan Suleimanov

Int. J. Circuit Theory Appl., 2014

2010

Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints.

Igor Lemberski, Petr Fiser

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Asynchronous two-level logic of reduced cost.

Igor Lemberski, Petr Fiser

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2007

Avoiding Hazards for Speed-Independent Logic Design.

Igor Lemberski

Proceedings of the World Congress on Engineering, 2007

Cost Effective Implementation of Asynchronous Two-Level Logic.

Igor Lemberski

Proceedings of the World Congress on Engineering, 2007

2002

Optimal Two-Level Delay - Insensitive Implementation of Logic Functions.

Igor Lemberski, Mark B. Josephs

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

1999

Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs.

Igor Lemberski

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

XILINX4000 Architecture-Driven Synthesis for Speed.

Igor Lemberski, M. Ratniece

Proceedings of the Field-Programmable Logic and Applications, 1998

Modified Approach to Automata State Encoding for LUT FPGA Implementation.

Igor Lemberski

Proceedings of the 24th EUROMICRO '98 Conference, 1998