Ignacio Algredo-Badillo
Orcid: 0000-0002-4748-3500
According to our database1,
Ignacio Algredo-Badillo
authored at least 32 papers
between 2006 and 2024.
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Bibliography
2024
Comput. Sci. Inf. Syst., 2024
2023
White-Box Adversarial Attacks Against Sentiment-Analysis Models using an Aspect-Based Approach.
Proceedings of the International Congress on Education and Technology in Sciences, 2023
2022
An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy.
Sensors, 2022
Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models.
Sensors, 2022
A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors.
Sensors, 2022
Int. J. Comput. Vis. Robotics, 2022
2021
CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions.
Sensors, 2021
Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES.
Sensors, 2021
A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks.
J. Sensors, 2021
J. Circuits Syst. Comput., 2021
2020
A Metaheuristic Optimization Approach for Parameter Estimation in Arrhythmia Classification from Unbalanced Data.
Sensors, 2020
A fuzzy petri net model for assessing analogical reasoning in children ranging from 5 to 8 years old.
J. Intell. Fuzzy Syst., 2020
2019
Real time FPGA-ANN architecture for outdoor obstacle detection focused in road safety.
J. Intell. Fuzzy Syst., 2019
IET Circuits Devices Syst., 2019
2018
J. Intell. Fuzzy Syst., 2018
IEICE Trans. Inf. Syst., 2018
2017
A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
2015
A comparative study of the wavenet PID controllers for applications in non-linear systems.
Proceedings of the 12th International Conference on Electrical Engineering, 2015
2014
Comput. Electr. Eng., 2014
2013
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256.
Microprocess. Microsystems, 2013
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
2012
Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation.
J. Circuits Syst. Comput., 2010
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard.
Comput. Electr. Eng., 2010
2009
An area/performance trade-off analysis of a GF(2<sup>m</sup>) multiplier architecture for elliptic curve cryptography.
Comput. Electr. Eng., 2009
Proceedings of the 2009 Mexican International Conference on Computer Science, 2009
2008
Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description.
IEICE Trans. Inf. Syst., 2008
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
2006
Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture.
Proceedings of the Computational Science and Its Applications, 2006