Ibtissem Seghaier
Orcid: 0000-0002-8934-9844
According to our database1,
Ibtissem Seghaier
authored at least 9 papers
between 2013 and 2020.
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Bibliography
2020
Mating Sensitivity Analysis and Statistical Verification for Efficient Yield Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2018
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
2017
Proceedings of the Verification and Evaluation of Computer and Communication Systems, 2017
2016
Cross recurrence verification technique for process variation-resilient analog circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Statistically Validating the Impact of Process Variations on Analog and Mixed Signal Designs.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
2013
Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2013