Ibrahim N. Hajj

According to our database1, Ibrahim N. Hajj authored at least 95 papers between 1987 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

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Bibliography

2017
Beyond SPICE.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015
On Device Modeling for Circuit Simulation With Application to Carbon-Nanotube and Graphene Nano-Ribbon Field-Effect Transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2012
Extended Nodal Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2004
Postroute gate sizing for crosstalk noise reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
Early probabilistic noise estimation for capacitively coupled interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Post-route gate sizing for crosstalk noise reduction.
Proceedings of the 40th Design Automation Conference, 2003

2002
A technique for Improving dual-output domino logic.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Estimation of state line statistics in sequential circuits.
ACM Trans. Design Autom. Electr. Syst., 2002

Pre-route Noise Estimation in Deep Submicron Integrated Circuits.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .
Proceedings of the 2002 Design, 2002

2001
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Maximum voltage variation in the power distribution network of VLSI circuits with RLC models.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Maximum power supply noise estimation in VLSI circuits using multimodal genetic algorithms.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits.
Proceedings of the 38th Design Automation Conference, 2001

2000
Architectural and compiler techniques for energy reduction in high-performance microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Using dynamic cache management techniques to reduce energy in general purpose processors.
IEEE Trans. Very Large Scale Integr. Syst., 2000

An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Power Bus Maximum Voltage Drop in Digital VLSI Circuits.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Instruction scheduling for low power on dynamically variable voltage processors.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

A hierarchical based approach for coupling aware delay analysis of combinational logic blocks.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

An analytical model for delay and crosstalk estimation in interconnects under general switching conditions.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

Current-Mode Threshold Logic Gates.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Simulation and Optimization of the Power Distribution Network in VLSI Circuits.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Peak current estimation for digital filters.
Proceedings of the IEEE International Conference on Acoustics, 2000

High-performance bidirectional repeaters.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999
Information-theoretic bounds on average signal transition activity [VLSI systems].
IEEE Trans. Very Large Scale Integr. Syst., 1999

A coding framework for low-power address and data busses.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Design error diagnosis and correction via test vector simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

An optimization technique for dual-output domino logic.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Using dynamic cache management techniques to reduce energy in a high-performance processor.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Correcting multiple design errors in digital VLSI circuits.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Low-power distributed arithmetic architectures using nonuniform memory partitioning.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A reduced-order scheme for coupled lumped-distributed interconnect simulation.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

An analytical, transistor-level energy model for SRAM-based caches.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A hybrid approach to design error detection and correction [VLSI digital circuits].
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Energy and Performance Improvements in Microprocessor Design Using a Loop Cache.
Proceedings of the IEEE International Conference On Computer Design, 1999

An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Estimation of maximum current envelope for power bus analysis and design.
Proceedings of the 1998 International Symposium on Physical Design, 1998

Decorrelating (DECOR) transformations for low-power adaptive filters.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Maximum Current Estimation in Programmable Logic Arrays.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997
Diagnosis and correction of multiple logic design errors in digital circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1997

Analytical estimation of signal transition activity from word-level statistics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Achievable bounds on signal transition activity.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Monte-Carlo approach for power estimation in sequential circuits.
Proceedings of the European Design and Test Conference, 1997

Analytical Estimation of Transition Activity From Word-Level Signal Statistics.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Computer-aided redesign of VLSI circuits for hot-carrier reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1995
Circuit-level dictionaries of CMOS bridging faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Timing and area optimization for standard-cell VLSI circuit design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Power Estimation in Sequential Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Logic design error diagnosis and correction.
IEEE Trans. Very Large Scale Integr. Syst., 1994

A probabilistic timing approach to hot-carrier effect estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Delay and area optimization for compact placement by gate resizing and relocation.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993
Switch-level timing simulation of bipolar ECL circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Efficient Variable Ordering Heuristics for Shared ROBDD.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Diagnosis and Correction of Logic Design Errors in Digital Circuits.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Simulation of physical faults in VLSI circuits.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Maximum Current Estimation in CMOS Circuits.
Proceedings of the 29th Design Automation Conference, 1992

1991
An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A Switch-Level Matrix Approach to Transistor-Level Fault Simulation.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
The complexity of fault detection in MOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

A multilevel parallel solver for block tridiagonal and banded linear systems.
Parallel Comput., 1990

A metal - metal matrix cell generator for multi-level metal MOS technology.
Integr., 1990

High speed VLSI logic simulation using bitwise operations and parallel processing.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

An Algebra for Switch-Level Simulation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
Switching network logic approach to sequential MOS circuit design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Parallel-concurrent fault simulation.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

Electromigration median time-to-failure based on a stochastic current waveform.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

Automatic mixed-mode timing simulation.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Computation of bus current variance for reliability estimation of VLSI circuits.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

A custom cell generation system for double-metal CMOS technology.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
iEDISON: an interactive statistical design tool for MOS VLSI circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

A tabular macromodeling approach to fast timing simulation including parasitics.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

CREST-a current estimator for CMOS circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

iPRIDE: a parallel integrated circuit simulator using direct method.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Delay Modeling and Time of Bipolar Digital Circuits.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Switch-Level Logic Simulation of Digital Bipolar Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987


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