Ibrahim Hur

According to our database, Ibrahim Hur authored at least 46 papers between 2004 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

Accurate and Scalable Many-Node Simulation.

Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur

CoRR, 2024

HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures.

Gerasimos Gerogiannis, Sriram Aananthakrishnan, Josep Torrellas, Ibrahim Hur

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023

The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor.

Sriram Aananthakrishnan, Shamsul Abedin, Vincent Cavé, Fabio Checconi, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Wim Heirman, Jason Howard, Ibrahim Hur, Samkit Jain, Marek M. Landowski, Kevin Ma, Jarrod A. Nelson, Robert Pawlowski, Fabrizio Petrini, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche

IEEE Micro, 2023

Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation.

Stijn Eyerman, Sam Van den Steen, Wim Heirman, Ibrahim Hur

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

2022

Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study.

Stijn Eyerman, Ibrahim Hur

CoRR, 2022

DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks.

Stijn Eyerman, Wim Heirman, Ibrahim Hur

Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Towards a GraphBLAS Implementation for Go.

Pascal Costanza, Ibrahim Hur, Timothy G. Mattson

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

2021

Automatic Sublining for Efficient Sparse Memory Accesses.

Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur

ACM Trans. Archit. Code Optim., 2021

RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors.

Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur

IEEE Comput. Archit. Lett., 2021

Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model.

Stijn Eyerman, Wim Heirman, Ibrahim Hur

IEEE Comput. Archit. Lett., 2021

Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions.

Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020

PIUMA: Programmable Integrated Unified Memory Architecture.

Sriram Aananthakrishnan, Nesreen K. Ahmed, Vincent Cavé, Marcelo Cintra, Yigit Demir, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Ivan Ganev, Wim Heirman, Hans-Christian Hoppe, Jason Howard, Ibrahim Hur, Midhunchandra Kodiyath, Samkit Jain, Daniel S. Klowden, Marek M. Landowski, Laurent Montigny, Ankit More, Przemyslaw Ossowski, Robert Pawlowski, Nick Pepperling, Fabrizio Petrini, Mariusz Sikora, Balasubramanian Seshasayee, Shaden Smith, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche, Izajasz P. Wrosz

CoRR, 2020

Breaking In-Order Branch Miss Recovery.

Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur

IEEE Comput. Archit. Lett., 2020

Hash Table Scalability on Intel PIUMA.

Balasubramanian Seshasayee, Joshua B. Fryman, Ibrahim Hur

Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

Projecting Performance for PIUMA using Down-Scaled Simulation.

Stijn Eyerman, Wim Heirman, Yigit Demir, Kristof Du Bois, Ibrahim Hur

Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

Efficient Sparse Matrix-Vector Multiplication on Intel PIUMA Architecture.

Sriram Aananthakrishnan, Robert Pawlowski, Joshua B. Fryman, Ibrahim Hur

Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2018

Multi-Stage CPI Stacks.

Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur

IEEE Comput. Archit. Lett., 2018

Many-core graph workload analysis.

Stijn Eyerman, Wim Heirman, Kristof Du Bois, Joshua B. Fryman, Ibrahim Hur

Proceedings of the International Conference for High Performance Computing, 2018

Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks.

Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors.

Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, Ibrahim Hur

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017

Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms.

Ancy Sarah Tom, Narayanan Sundaram, Nesreen K. Ahmed, Shaden Smith, Stijn Eyerman, Midhunchandra Kodiyath, Ibrahim Hur, Fabrizio Petrini, George Karypis

Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2015

Initial results on computational performance of Intel many integrated core, sandy bridge, and graphical processing unit architectures: implementation of a 1D c++/OpenMP electrostatic particle-in-cell code.

A. Vapirev, Jan Deca, Giovanni Lapenta, Stefano Markidis, Ibrahim Hur, Jean-Luc Cambier

Concurr. Comput. Pract. Exp., 2015

2014

An Evaluation of High-Level Mechanistic Core Models.

Trevor E. Carlson, Wim Heirman, Stijn Eyerman, Ibrahim Hur, Lieven Eeckhout

ACM Trans. Archit. Code Optim., 2014

Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor.

Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout

Proceedings of the 4th International Workshop on Runtime and Operating Systems for Supercomputers, 2014

Undersubscribed threading on clustered cache architectures.

Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2012

Hardware transactional memory with software-defined conflicts.

J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero

ACM Trans. Archit. Code Optim., 2012

Resource-bounded multicore emulation using Beefarm.

Oriol Arcas, Nehir Sönmez, Gokhan Sayilar, Satnam Singh, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero

Microprocess. Microsystems, 2012

Circuit design of a dual-versioning L1 data cache.

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero

Integr., 2012

Profiling and Optimizing Transactional Memory Applications.

Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero

Int. J. Parallel Program., 2012

Power-aware multi-core simulation for early design stage hardware/software co-optimization.

Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only).

Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero

SIGMETRICS Perform. Evaluation Rev., 2011

RMS-TM: a comprehensive benchmark suite for transactional memory systems.

Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero

Proceedings of the ICPE'11, 2011

Circuit design of a dual-versioning L1 data cache for optimistic concurrency.

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System.

Nehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype.

Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory.

Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems.

Gokcen Kestor, Roberto Gioiosa, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.

Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

The Velox Transactional Memory Stack.

Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Rivière, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrián Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, Torvald Riegel

IEEE Micro, 2010

Discovering and understanding performance bottlenecks in transactional applications.

Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009

Feedback mechanisms for improving probabilistic memory prefetching.

Ibrahim Hur, Calvin Lin

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008

A comprehensive approach to DRAM power management.

Ibrahim Hur, Calvin Lin

Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007

Memory scheduling for modern microprocessors.

Ibrahim Hur, Calvin Lin

ACM Trans. Comput. Syst., 2007

2006

Adaptive History-Based Memory Schedulers for Modern Processors.

Ibrahim Hur, Calvin Lin

IEEE Micro, 2006

Memory Prefetching Using Adaptive Stream Detection.

Ibrahim Hur, Calvin Lin

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

2004

Adaptive History-Based Memory Schedulers.

Ibrahim Hur, Calvin Lin

Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004