Ian P. Jalowiecki

According to our database, Ian P. Jalowiecki authored at least 9 papers between 1988 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2001

A programmable processor with 4096 processing units for media applications.

Argy Krikelis, Ian P. Jalowiecki, David L. Bean, Ryan Bishop, M. Facey, D. Boughton, S. Murphy, M. Whitaker

Proceedings of the IEEE International Conference on Acoustics, 2001

1996

The Prediction of Circuit Performance Variations for Deep Submicron CMOS Processes.

Thomas Gneiting, Ian P. Jalowiecki

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Economics Modelling and Optimisation of MCM Test Strategies.

Chryssa Dislis, Ian P. Jalowiecki

Proceedings of the 1996 European Design and Test Conference, 1996

1995

MCM Quality and Cost Analysis Using Economics Models.

Chryssa Dislis, A. F. Al-Ani, Ian P. Jalowiecki

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

An Implementation Of A Set Mode For Prolog On A Parallell Associative Processor.

Darren Patrick Rodohan, Ray J. Glover, Ian P. Jalowiecki

Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

1993

The implementation of a MCM associative string processor.

Claus M. Habiger, Ian P. Jalowiecki

Proceedings of the VLSI 93, 1993

1991

Associative massively parallel computers.

R. Mike Lea, Ian P. Jalowiecki

Proc. IEEE, 1991

The WASP 2 Wafer Scale Integration Demonstrator.

Ian P. Jalowiecki, Stephen J. Hedge

Proceedings of the VLSI 91, 1991

1988

A 9-kbit associative memory for high-speed parallel processing applications.

Simon R. Jones, Ian P. Jalowiecki, Stephen J. Hedge, R. Mike Lea

IEEE J. Solid State Circuits, April, 1988