Ian Galton

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024

A 2.5-20kSps in-Pixel Direct Digitization Front-End for ECoG with In-Stimulation Recording.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

Adaptive Cancellation of Inter-Symbol Interference in High-Speed Continuous-Time DACs.

[BibT_eX]

[DOI]

Subin Kim

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

2022

DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional-N PLLs.

[BibT_eX]

[DOI]

Eslam Helal

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs.

[BibT_eX]

[DOI]

Jason Remple

IEEE J. Solid State Circuits, 2022

2021

Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL.

[BibT_eX]

[DOI]

Eslam Helal

IEEE J. Solid State Circuits, 2021

Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs.

[BibT_eX]

[DOI]

Eslam Helal

IEEE J. Solid State Circuits, 2021

2020

MSE Analysis of a Multi-Loop LMS Pseudo-Random Noise Canceler for Mixed-Signal Circuit Calibration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019

Subsampling Mismatch Noise Cancellation for High-Speed Continuous-Time DACs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error.

[BibT_eX]

[DOI]

Kevin Rivas-Rivera

IEEE J. Solid State Circuits, 2019

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

Adaptive Cancellation of Static and Dynamic Mismatch Error in Continuous-Time DACs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017

The Effects of Inter-Symbol Interference in Dynamic Element Matching DACs.

[BibT_eX]

[DOI]

Jason Remple

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

Simplified Logic for Tree-Structure Segmented DEM Encoders.

[BibT_eX]

[DOI]

Jason Remple

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional-N PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015

A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Quantization Noise Cancellation for FDC-Based Fractional-N PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion.

[BibT_eX]

[DOI]

Guobi Zhao

IEEE J. Solid State Circuits, 2015

Errata for "A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO".

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation.

[BibT_eX]

[DOI]

Guobi Zhao

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013

A Class of Quantizers With DC-Free Quantization Noise and Optimal Immunity to Nonlinearity-Induced Spurious Tones.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2013

A Fundamental Limitation of DC-Free Quantization Noise With Respect To Nonlinearity-Induced Spurious Tones.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2013

Delta-Sigma FDC Based Fractional-N PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction.

[BibT_eX]

[DOI]

Nevena Rakuljic

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

2012

A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

2011

A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Correction to "A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC" [Nov 10 2250-2261].

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

2010

Tree-Structured DEM DACs with Arbitrary Numbers of Levels.

[BibT_eX]

[DOI]

Nevena Rakuljic

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Why Dynamic-Element-Matching DACs Work.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A mostly digital variable-rate continuous-time ADC ΔΣ modulator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

CMOS phase-locked loops for frequency synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Low-voltage analog and mixed-signal CMOS circuit design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion.

[BibT_eX]

[DOI]

Kok Lim Chan

Nevena Rakuljic

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs.

[BibT_eX]

[DOI]

Kok Lim Chan

Jianyu Zhu

IEEE J. Solid State Circuits, 2008

Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Short Course.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A Digital Requantizer With Shaped Requantization Noise That Remains Well Behaved After Nonlinear Distortion.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2007

Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

LSB Dithering in MASH Delta-Sigma D/A Converters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS.

[BibT_eX]

[DOI]

Matt Miller

Robert Bogdan Staszewski

Bram Nauta

Michiel Steyaert

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

Digital Background Correction of Harmonic Distortion in Pipelined ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching.

[BibT_eX]

[DOI]

Kok Lim Chan

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Addition to "A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation".

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

2004

A tight signal-band power bound on mismatch noise in a mismatch-shaping digital-to-analog converter.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 2004

Techniques for phase noise suppression in recirculating DLLs.

[BibT_eX]

[DOI]

Sheng Ye

IEEE J. Solid State Circuits, 2004

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC.

[BibT_eX]

[DOI]

Eric Siragusa

IEEE J. Solid State Circuits, 2004

A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

2003

Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Techniques for in-band phase noise suppression in re-circulating DLLs.

[BibT_eX]

[DOI]

Sheng Ye

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

A multiple-crystal interface PLL with VCO realignment to reduce phase noise.

[BibT_eX]

[DOI]

Sheng Ye

IEEE J. Solid State Circuits, 2002

A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2002

A necessary and sufficient condition for mismatch shaping in multi-bit DACs.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Segmented mismatch-shaping D/A conversion.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2001

The mismatch-noise PSD from a tree-structured DAC in a second-order ΔΣ modulator with a midscale input.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2001

2000

A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999

A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs.

[BibT_eX]

[DOI]

Henrik Jensen

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

An area-efficient differential input ADC with digital common mode rejection.

[BibT_eX]

[DOI]

Henrik Jensen

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINAD.

[BibT_eX]

[DOI]

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

A Nyquist-rate delta-sigma A/D converter.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1998

A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1998

1995

A Robust Parallel Delta-Sigma A/D Converter Architecture.

[BibT_eX]

[DOI]

Henrik T. Jensen

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A Practical Second-Order Delta-Digma Frequency-to-Digital Converter.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

Granular quantization noise in a class of delta-sigma modulators.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 1994

Higher-Order Delta-Sigma Frequency to Digital Conversion.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Granular quantization noise in the first-order delta-sigma modulator.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 1993

Combined RF Phase Extraction and Digitalization.

[BibT_eX]

George Zimmerman

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

One-bit Dithering in Delta-Sigma Modulator-based D/A Conversion.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1989

An efficient three-point arc algorithm.

[BibT_eX]

[DOI]