Ian G. Harris

Affiliations:
  • University of California, Irvine, USA


According to our database1, Ian G. Harris authored at least 81 papers between 1991 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
ShareLoRA: Parameter Efficient and Robust Large Language Model Fine-tuning via Shared Low-Rank Adaptation.
CoRR, 2024

2023
LinguaLinked: A Distributed Large Language Model Inference System for Mobile Devices.
CoRR, 2023

Robust Safety Classifier for Large Language Models: Adversarial Prompt Shield.
CoRR, 2023

FuzzLLM: A Novel and Universal Fuzzing Framework for Proactively Discovering Jailbreak Vulnerabilities in Large Language Models.
CoRR, 2023

A Graph-to-Sequence Model for Joint Intent Detection and Slot Filling.
Proceedings of the 17th IEEE International Conference on Semantic Computing, 2023

PCMID: Multi-Intent Detection through Supervised Prototypical Contrastive Learning.
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2023, 2023

GAP-Gen: Guided Automatic Python Code Generation.
Proceedings of the 17th Conference of the European Chapter of the Association for Computational Linguistics: EACL 2023, 2023

2022
Mitra Behzadi at SemEval-2022 Task 5 : Multimedia Automatic Misogyny Identification method based on CLIP.
Proceedings of the 16th International Workshop on Semantic Evaluation, SemEval@NAACL 2022, 2022

GraphMemDialog: Optimizing End-to-End Task-Oriented Dialog Systems Using Graph Memory Networks.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021
Rapid Cyber-bullying detection method using Compact BERT Models.
Proceedings of the 15th IEEE International Conference on Semantic Computing, 2021

Spoken Language Understanding for Task-oriented Dialogue Systems with Augmented Memory Networks.
Proceedings of the 2021 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies, 2021

Zero Footprint Opaque Predicates: Synthesizing Opaque Predicates from Naturally Occurring Invariants.
Proceedings of the Detection of Intrusions and Malware, and Vulnerability Assessment, 2021

Detecting Telephone-based Social Engineering Attacks using Scam Signatures.
Proceedings of the IWSPA@CODASPY 2021: ACM Workshop on Security and Privacy Analytics, 2021

2020
A Study of Targeted Telephone Scams Involving Live Attackers.
Proceedings of the Socio-Technical Aspects in Security and Trust, 2020

Analysis of Online Conversations to Detect Cyberpredators Using Recurrent Neural Networks.
Proceedings of the Proceedings for the First International Workshop on Social Threats in Online Conversations: Understanding and Management, 2020

2019
Scam Detection Assistant: Automated Protection from Scammers.
Proceedings of the First International Conference on Societal Automation, 2019

Chatbot-based assertion generation from natural language specifications.
Proceedings of the 2019 Forum for Specification and Design Languages, 2019

Automatic Assertion Generation from Natural Language Specifications Using Subtree Analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Detecting Phishing Attacks Using Natural Language Processing and Machine Learning.
Proceedings of the 12th IEEE International Conference on Semantic Computing, 2018

2017
An efficient approach to prevent Battery Exhaustion Attack on BLE-based mesh networks.
Proceedings of the 2017 International Conference on Computing, 2017

Designing cyber-physical systems from natural language descriptions.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

2016
A residual battery-aware routing algorithm based on DSR for BLE sensor networks.
Proceedings of the 2016 Wireless Telecommunications Symposium, 2016

Detection of Social Engineering Attacks Through Natural Language Processing of Conversations.
Proceedings of the Tenth IEEE International Conference on Semantic Computing, 2016

Multilevel design understanding: from specification to logic (invited paper).
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

GLAsT: Learning formal grammars to translate natural language specifications into hardware assertions.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
An on-demand scatternet formation and multi-hop routing protocol for BLE-based wireless sensor networks.
Proceedings of the 2015 IEEE Wireless Communications and Networking Conference, 2015

Generating formal hardware verification properties from Natural Language documentation.
Proceedings of the 9th IEEE International Conference on Semantic Computing, 2015

Semantic analysis of dialogs to detect social engineering attacks.
Proceedings of the 9th IEEE International Conference on Semantic Computing, 2015

2014
Control-flow checking for intrusion detection via a real-time debug interface.
Proceedings of the International Conference on Smart Computing, 2014

Automating the translation of assertions using natural language processing techniques.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

2013
Task-Driven Software Summarization.
Proceedings of the 2013 IEEE International Conference on Software Maintenance, 2013

2012
Hardware-Assisted Detection of Malicious Software in Embedded Systems.
IEEE Embed. Syst. Lett., 2012

Test generation for subtractive specification errors.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Adaptable intrusion detection using partial runtime reconfiguration.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Automatic generation of Verilog bus transactors from natural language protocol specifications.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Generating formal system models from natural language descriptions.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Minimization of Trojan footprint by reducing Delay/Area impact.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Extracting design information from natural language specifications.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2009
Security testing of session initiation protocol implementations.
ISC Int. J. Inf. Secur., 2009

2008
Evaluation of an efficient control-oriented coverage metric.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

2007
A CLP-Based Functional ATPG for Extended FSMs.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Automatic generation of functional coverage models from CTL.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Improving feasible interactions among multiple processes.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Guest Editor's Introduction to the Special Section on Simulation-Based Design Validation.
IEEE Trans. Computers, 2006

Guest Editor's Introduction.
Int. J. Parallel Program., 2006

Error Detection Using Model Checking vs. Simulation.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

A coverage metric for the validation of interacting processes.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Introduction.
ACM Trans. Design Autom. Electr. Syst., 2005

Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test.
IEEE Trans. Computers, 2005

Editorial.
Int. J. Parallel Program., 2005

Design validation of behavioral VHDL descriptions for arbitrary fault models.
Proceedings of the 10th European Test Symposium, 2005

An efficient control-oriented coverage metric.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
ITC 2003 panels: Part 1.
IEEE Des. Test Comput., 2004

Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s.
Proceedings of the 2004 Design, 2004

2003
Partial BIST insertion to eliminate data correlation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems.
J. Circuits Syst. Comput., 2003

Fault Models and Test Generation for Hardware-Software Covalidation.
IEEE Des. Test Comput., 2003

A Deterministic Globally Asynchronous Locally Synchronousy Microprocessor Architecture.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

The Confluence of Manufacturing Test and Design Validation.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Application of Built in Self-Test for Interconnect Testing of FPGAs.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

A method for the evaluation of behavioral fault models.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Fast Computation of Data Correlation Using BDDs.
Proceedings of the 2003 Design, 2003

2002
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Test generation for hardware-software covalidation using non-linear programming.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

ATPG for timing-induced functional errors on trigger events in hardware-software systems.
Proceedings of the 7th European Test Workshop, 2002

2001
A validation fault model for timing-induced functional errors.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

BIST-based delay path testing in FPGA architectures.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Hardware-software covalidation: fault models and test generation.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Test pattern generation for timing-induced functional errors in hardware-software systems.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

2000
A domain coverage metric for the validation of behavioral VHDL descriptions.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A Data Flow Fault Coverage Metric for Validation of Behavioral HDL Descriptions.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Interconnect testing in cluster-based FPGA architectures.
Proceedings of the 37th Conference on Design Automation, 2000

1997
Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction.
VLSI Design, 1997

1994
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Microarchitectural Synthesis of VLSI Designs with High Test Concurrency.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Intertwined Scheduling, Module Selection and Allocation in Time-and-Area.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Test Path Generation and Test Scheduling for Self-Testable Designs.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1991
A Testbed for Managing Digital Video and Audio Storage.
Proceedings of the Summer 1991 USENIX Conference, Nashville, TE, USA, June 1991, 1991


  Loading...