Iaçanã I. Weber

According to our database1, Iaçanã I. Weber authored at least 12 papers between 2018 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2018
2019
2020
2021
2022
2023
2024
2025
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4
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2
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2

Legend:

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In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2025
Reinforcement learning for thermal and reliability management in manycore systems.
Des. Autom. Embed. Syst., March, 2025

2024
Enhancing Manycore Lifetime Through Reinforcement Learning Task Mapping and Migration.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

2023
FLEA - FIT-Aware Heuristic for Application Allocation in Many-Cores based on Q-Learning.
Proceedings of the XIII Brazilian Symposium on Computing Systems Engineering, 2023

2022
A High-level Model to Leverage NoC-based Many-core Research.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Reliability Assessment of Many-Core Dynamic Thermal Management.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Hardware Accelerator for Runtime Temperature Estimation in Many-Cores.
IEEE Des. Test, 2021

Chronos: An Abstract NoC-based Manycore with Preserved Temporal and Spatial Traffic Distribution.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Dynamic Thermal Management in Many-Core Systems Leveraged by Abstract Modeling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Open-Source NoC-Based Many-Core for Evaluating Hardware Trojan Detection Methods.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018
Exploring Asynchronous End-to-End Communication Through a Synchronous NoC.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Exploring RSA Performance up to 4096-bit for Fast Security Processing on a Flexible Instruction Set Architecture Processor.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018


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