I-Min Liu

According to our database, I-Min Liu authored at least 18 papers between 1999 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

Technology mapping with crosstalk noise avoidance.

Fang-Yu Fan, Hung-Ming Chen, I-Min Liu

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2007

Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement.

Huaizhi Wu, Martin D. F. Wong, I-Min Liu, Yusu Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.

Hung-Ming Chen, I-Min Liu, Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Timing-constrained and voltage-island-aware voltage assignment.

Huaizhi Wu, Martin D. F. Wong, I-Min Liu

Proceedings of the 43rd Design Automation Conference, 2006

2005

Simultaneous power supply planning and noise avoidance in floorplan design.

Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Wire Planning with Bounded Over-the-Block Wires.

Hua Xiang, I-Min Liu, Martin D. F. Wong

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Post-placement voltage island generation under performance requirement.

Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout].

Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.

Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003

Floorplanning with power supply noise avoidance.

Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem.

Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu

Proceedings of the 2002 Design, 2002

2001

Integrated power supply planning and floorplanning.

I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong

Proceedings of ASP-DAC 2001, 2001

2000

Simultaneous routing and buffer insertion with restrictions onbuffer locations.

Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion.

I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong

Proceedings of the 2000 International Symposium on Physical Design, 2000

Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing.

I-Min Liu, Adnan Aziz

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Meeting Delay Constraints in DSM by Minimal Repeater Insertion.

I-Min Liu, Adnan Aziz, D. F. Wong

Proceedings of the 2000 Design, 2000

1999

An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation.

I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou

Proceedings of the IEEE International Conference On Computer Design, 1999

Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations.

Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz

Proceedings of the 36th Conference on Design Automation, 1999