Hyuntak Jeon
Orcid: 0000-0003-0537-8494
According to our database1,
Hyuntak Jeon
authored at least 16 papers
between 2017 and 2024.
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Bibliography
2024
A Wide-Dynamic-Range, DC-Coupled, Time-Based Neural-Recording IC With Optimized CCO Frequency.
IEEE Access, 2024
An Area-Efficient, DC-Coupled VCO-Based CT ΔΣM with Input-TR-DAC for Neural Recording.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
A Sub-aF Super-High-Resolution Capacitance-to-Digital Converter with a Bandpass ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
A Wide-Dynamic-Range Neural-Recording IC With Automatic-Gain-Controlled AFE and CT Dynamic-Zoom ΔΣ ADC for Saturation-Free Closed-Loop Neural Interfaces.
IEEE J. Solid State Circuits, 2022
An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 99.5dB-DR 5kHz-BW Closed-Loop Neural-Recording IC based on Continuous-Time Dynamic-Zoom ΔΣ ADC with Automatic AFE-Gain Control.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A CMRR Enhancement Circuit Employing Gₘ-Controllable Output Stages for Capacitively Coupled Instrumentation Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A Power-Efficient Radiation Sensor Interface with a Peak-Triggered Sampling Scheme for Mobile Dosimeters.
Sensors, 2020
2019
A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface.
IEEE J. Solid State Circuits, 2019
A 100Mb/s Galvanically-Coupled Body-Channel-Communication Transceiver with 4.75pJ/b TX and 26.8 pJ/b RX for Bionic Arms.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A neural recording amplifier based on adaptive SNR optimization technique for long-term implantation.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017