Hyunsub Norbert Rie
Orcid: 0000-0003-0891-458X
According to our database1,
Hyunsub Norbert Rie
authored at least 4 papers
between 2020 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2020
IEEE Access, 2020