Hyunsu Chae

According to our database, Hyunsu Chae authored at least 10 papers between 2004 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

ML-Assisted RF IC Design Enablement: the New Frontier of AI for EDA.

Hyunsu Chae, Song Hang Chai, Taiyun Chi, Sensen Li, David Z. Pan

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design.

Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization.

Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Jisu Yook, Jihoon Lee, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sungsik Park, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim, Sung-Ung Kwak

IEEE J. Solid State Circuits, January, 2024

ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning.

Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zixuan Jiang, Daniel De Araujo, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, David Z. Pan

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization.

Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET.

Soo-Min Lee, Jihoon Lim, Jaehyuk Jang, Hyoungjoong Kim, Kyunghwan Min, Woongki Min, Hyeonji Han, Gyusik Kim, Jaeyoung Kim, Chulho Kim, Sejun Jeon, Jinhoon Park, Hyunsu Chae, Sangwook Han, Hiep Pham, Xingliang Zhao, Qilin Gu, Chih-Wei Yao, Sangho Kim, Jongwoo Lee

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2018

Test cost reduction for <i>X</i>-value elimination by scan slice correlation analysis.

Hyunsu Chae, Joon-Sung Yang

Proceedings of the 55th Annual Design Automation Conference, 2018

2005

A Fast Hopping Frequency Synthesizer for UWB Systems in a CMOS Technology.

Hyunsu Chae, Eun-Chul Park, Choong-Yul Cha, Jungeun Lee, Chun-Deok Suh, Jeongwook Koh, Hanseung Lee, Hoon-Tae Kim

Proceedings of the 2nd IEEE International Symposium on Wireless Communication Systems, 2005

2004

High speed mixed analog/digital PRML architecture for optical data storage system.

Maxim Konakov, Jae-Wook Lee, Junghyun Lee, Eun-Jin Ryu, Eingseob Cho, Jungeun Lee, Hyunsu Chae, Jeongwon Lee

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

An improved architecture of the mixed mode clock/data recovery for DVD read channel.

Jungeun Lee, Hyunsu Chae, Hanseung Lee, Maxim Konakov, Junghyun Lee, Jeongwon Lee

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004