Hyunok Oh
Orcid: 0000-0002-9044-7441
According to our database1,
Hyunok Oh
authored at least 87 papers
between 1996 and 2024.
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Bibliography
2024
IEEE Trans. Dependable Secur. Comput., 2024
zkVoting : Zero-knowledge proof based coercion-resistant and E2E verifiable e-voting system.
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
IEEE Access, 2024
Proceedings of the IEEE International Conference on Blockchain, 2024
Proceedings of the 19th ACM Asia Conference on Computer and Communications Security, 2024
2023
Proceedings of the Computer Security - ESORICS 2023, 2023
2021
IACR Cryptol. ePrint Arch., 2021
2020
Combinatorial Subset Difference - IoT-Friendly Subset Representation and Broadcast Encryption.
Sensors, 2020
IACR Cryptol. ePrint Arch., 2020
Practical Verifiable Computation by Using a Hardware-Based Correct Execution Environment.
IEEE Access, 2020
2019
AuthCropper: Authenticated Image Cropper for Privacy Preserving Surveillance Systems.
ACM Trans. Embed. Comput. Syst., 2019
Inf. Sci., 2019
IACR Cryptol. ePrint Arch., 2019
SIMS : Self Sovereign Identity Management System with Preserving Privacy in Blockchain.
IACR Cryptol. ePrint Arch., 2019
SAVER: Snark-friendly, Additively-homomorphic, and Verifiable Encryption and decryption with Rerandomization.
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
Proceedings of the ICT Systems Security and Privacy Protection, 2019
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019
2018
Real Time Syst., 2018
Forward-secure ID based digital signature scheme with forward-secure private key generator.
Inf. Sci., 2018
AuthCropper: Authenticated Image Cropper for Privacy Preserving Surveillance Systems.
IACR Cryptol. ePrint Arch., 2018
Secure non-volatile memory with scratch pad memory using dual encryption mode: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018
2017
Multiprocessor Scheduling of a Multi-Mode Dataflow Graph Considering Mode Transition Delay.
ACM Trans. Design Autom. Electr. Syst., 2017
Combinatorial Subset Difference Public Key Broadcast Encryption Scheme for Secure Multicast.
IACR Cryptol. ePrint Arch., 2017
Forward-Secure Digital Signature Schemes with Optimal Computation and Storage of Signers.
Proceedings of the ICT Systems Security and Privacy Protection, 2017
A fast profiler for compilation of multi-threaded applications on a hybrid memory system.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 14th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2017
2016
Collaborative processing of data-intensive algorithms with CPU, intelligent SSD, and GPU.
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016
Multiprocessor Scheduling of an SDF Graph with Library Tasks Considering the Worst Case Contention Delay.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016
Proceedings of the 2016 International Conference on Big Data and Smart Computing, 2016
2015
IEEE Trans. Computers, 2015
On running data-intensive algorithms with intelligent SSD and host CPU: a collaborative approach.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015
Proceedings of the 2015 International Conference on Compilers, 2015
2014
Dynamic Behavior Specification and Dynamic Mapping for Real-Time Embedded Systems: HOPES Approach.
ACM Trans. Embed. Comput. Syst., 2014
IEEE Trans. Computers, 2014
2013
Decidable Dataflow Models for Signal Processing: Synchronous Dataflow and Its Extensions.
Proceedings of the Handbook of Signal Processing Systems, 2013
J. Signal Process. Syst., 2013
Failure-Aware Task Scheduling of Synchronous Data Flow Graphs Under Real-Time Constraints.
J. Signal Process. Syst., 2013
A lifetime aware buffer assignment method for streaming applications on DRAM/PRAM hybrid memory.
ACM Trans. Embed. Comput. Syst., 2013
An energy aware buffer mapping technique on hybrid STT-MRAM memories with multiple retention time for stream applications.
Des. Autom. Embed. Syst., 2013
Proceedings of the International Conference on Supercomputing, 2013
A novel analytical method for worst case response time estimation of distributed embedded systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 22nd ACM International Conference on Information and Knowledge Management, 2013
2012
A parallel and distributed meta-heuristic framework based on partially ordered knowledge sharing.
J. Parallel Distributed Comput., 2012
An ILP-based Worst-case Performance Analysis Technique for Distributed Real-time Embedded Systems.
Proceedings of the 33rd IEEE Real-Time Systems Symposium, 2012
A lifetime aware buffer assignment method for streaming applications on DRAM/PRAM hybrid memory (Extended abstract).
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
IEEE Trans. Ind. Informatics, 2011
Proceedings of the International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures, 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011
Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Cyberpsychology Behav. Soc. Netw., 2010
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
Decidable Signal Processing Dataflow Graphs: Synchronous and Cyclo-Static Dataflow Graphs.
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
2008
Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic Behavior.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
2006
PBPAIR: an energy-efficient error-resilient encoding using probability based power aware intra refresh.
ACM SIGMOBILE Mob. Comput. Commun. Rev., 2006
Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 25th International Conference on Distributed Computing Systems Workshops (ICDCS 2005 Workshops), 2005
Shift buffering technique for automatic code synthesis from synchronous dataflow graphs.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs.
Proceedings of the 2005 International Conference on Compilers, 2005
2004
J. VLSI Signal Process., 2004
2003
Memory-Optimized Software Synthesis from Dataflow Program Graphs with Large Size Data Samples.
EURASIP J. Adv. Signal Process., 2003
2002
Fractional rate dataflow model and efficient code synthesis for multimedia applications.
Proceedings of the 2002 Joint Conference on Languages, 2002
Proceedings of the 39th Design Automation Conference, 2002
Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002
2000
Proceedings of ASP-DAC 2000, 2000
1999
A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999
1996
Proceedings of the Euro-Par '96 Parallel Processing, 1996