Hyunok Oh

Orcid: 0000-0002-9044-7441

According to our database1, Hyunok Oh authored at least 89 papers between 1996 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
vCNN: Verifiable Convolutional Neural Network Based on zk-SNARKs.
IEEE Trans. Dependable Secur. Comput., 2024

zkVoting : Zero-knowledge proof based coercion-resistant and E2E verifiable e-voting system.
IACR Cryptol. ePrint Arch., 2024

sfLiLAC: Linear Prover, Logarithmic Verifier and Field-agnostic Multilinear Polynomial Commitment Scheme.
IACR Cryptol. ePrint Arch., 2024

Hadamard Product Arguments and Their Applications.
IACR Cryptol. ePrint Arch., 2024

zkMarket : Privacy-preserving Digital Data Trade System via Blockchain.
IACR Cryptol. ePrint Arch., 2024

Lego-DLC: batching module for commit-carrying SNARK under Pedersen Engines.
IACR Cryptol. ePrint Arch., 2024

DUPLEX: Scalable Zero-Knowledge Lookup Arguments over RSA Group.
IACR Cryptol. ePrint Arch., 2024

A Hardware-Based Correct Execution Environment Supporting Virtual Memory.
IEEE Access, 2024

GrAC: Graph-Based Anonymous Credentials from Identity Graphs on Blockchain.
Proceedings of the IEEE International Conference on Blockchain, 2024

zkLogis: Scalable, Privacy-Enhanced, and Traceable Logistics on Public Blockchain.
Proceedings of the 19th ACM Asia Conference on Computer and Communications Security, 2024

2023
Azeroth: Auditable Zero-Knowledge Transactions in Smart Contracts.
IEEE Access, 2023

Efficient Transparent Polynomial Commitments for zk-SNARKs.
Proceedings of the Computer Security - ESORICS 2023, 2023

2021
Privacy-preserving Identity Management System.
IACR Cryptol. ePrint Arch., 2021

Succinct Zero-Knowledge Batch Proofs for Set Accumulators.
IACR Cryptol. ePrint Arch., 2021

Forward-Secure Multi-User Aggregate Signatures Based on zk-SNARKs.
IEEE Access, 2021

2020
Combinatorial Subset Difference - IoT-Friendly Subset Representation and Broadcast Encryption.
Sensors, 2020

vCNN: Verifiable Convolutional Neural Network.
IACR Cryptol. ePrint Arch., 2020

Efficient Verifiable Image Redacting based on zk-SNARKs.
IACR Cryptol. ePrint Arch., 2020

Practical Verifiable Computation by Using a Hardware-Based Correct Execution Environment.
IEEE Access, 2020

Simulation-Extractable zk-SNARK With a Single Verification.
IEEE Access, 2020

2019
AuthCropper: Authenticated Image Cropper for Privacy Preserving Surveillance Systems.
ACM Trans. Embed. Comput. Syst., 2019

FAS: Forward secure sequential aggregate signatures for secure logging.
Inf. Sci., 2019

BESTIE: Broadcast Encryption Scheme for Tiny IoT Equipments.
IACR Cryptol. ePrint Arch., 2019

SIMS : Self Sovereign Identity Management System with Preserving Privacy in Blockchain.
IACR Cryptol. ePrint Arch., 2019

SAVER: Snark-friendly, Additively-homomorphic, and Verifiable Encryption and decryption with Rerandomization.
IACR Cryptol. ePrint Arch., 2019

QAP-based Simulation-Extractable SNARK with a Single Verification.
IACR Cryptol. ePrint Arch., 2019

Scalable Wildcarded Identity-Based Encryption.
IACR Cryptol. ePrint Arch., 2019

Forward Secure Identity-Based Signature Scheme with RSA.
Proceedings of the ICT Systems Security and Privacy Protection, 2019

AILocker: authenticated image locker for video.
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

SA-SPM: an efficient compiler for security aware scratchpad memory (invited paper).
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

2018
A hybrid performance analysis technique for distributed real-time embedded systems.
Real Time Syst., 2018

Forward-secure ID based digital signature scheme with forward-secure private key generator.
Inf. Sci., 2018

AuthCropper: Authenticated Image Cropper for Privacy Preserving Surveillance Systems.
IACR Cryptol. ePrint Arch., 2018

Secure non-volatile memory with scratch pad memory using dual encryption mode: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

2017
Multiprocessor Scheduling of a Multi-Mode Dataflow Graph Considering Mode Transition Delay.
ACM Trans. Design Autom. Electr. Syst., 2017

Combinatorial Subset Difference Public Key Broadcast Encryption Scheme for Secure Multicast.
IACR Cryptol. ePrint Arch., 2017

High-performance data mining with intelligent SSD.
Clust. Comput., 2017

Forward-Secure Digital Signature Schemes with Optimal Computation and Storage of Signers.
Proceedings of the ICT Systems Security and Privacy Protection, 2017

A fast profiler for compilation of multi-threaded applications on a hybrid memory system.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Hierarchical Dataflow Modeling of Iterative Applications.
Proceedings of the 54th Annual Design Automation Conference, 2017

PASS: Privacy aware secure signature scheme for surveillance systems.
Proceedings of the 14th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2017

2016
In-storage processing of database scans and joins.
Inf. Sci., 2016

Intelligent SSD: A turbo for big data mining.
Comput. Sci. Inf. Syst., 2016

Collaborative processing of data-intensive algorithms with CPU, intelligent SSD, and GPU.
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016

Multiprocessor Scheduling of an SDF Graph with Library Tasks Considering the Worst Case Contention Delay.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016

Data mining in intelligent SSD: Simulation-based evaluation.
Proceedings of the 2016 International Conference on Big Data and Smart Computing, 2016

2015
Optimal Checkpoint Selection with Dual-Modular Redundancy Hardening.
IEEE Trans. Computers, 2015

On running data-intensive algorithms with intelligent SSD and host CPU: a collaborative approach.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

Message from the Chairs.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Optimization of multi-channel BCH error decoding for common cases.
Proceedings of the 2015 International Conference on Compilers, 2015

2014
Dynamic Behavior Specification and Dynamic Mapping for Real-Time Embedded Systems: HOPES Approach.
ACM Trans. Embed. Comput. Syst., 2014

An Efficient Non-Linear Cost Compression Algorithm for Multi Level Cell Memory.
IEEE Trans. Computers, 2014

2013
Decidable Dataflow Models for Signal Processing: Synchronous Dataflow and Its Extensions.
Proceedings of the Handbook of Signal Processing Systems, 2013

Port Based Actor Model with Kahn Process Network Model and Decidable Dataflow Model.
J. Signal Process. Syst., 2013

Failure-Aware Task Scheduling of Synchronous Data Flow Graphs Under Real-Time Constraints.
J. Signal Process. Syst., 2013

A lifetime aware buffer assignment method for streaming applications on DRAM/PRAM hybrid memory.
ACM Trans. Embed. Comput. Syst., 2013

An energy aware buffer mapping technique on hybrid STT-MRAM memories with multiple retention time for stream applications.
Des. Autom. Embed. Syst., 2013

Active disk meets flash: a case for intelligent SSDs.
Proceedings of the International Conference on Supercomputing, 2013

A novel analytical method for worst case response time estimation of distributed embedded systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Intelligent SSD: a turbo for big data mining.
Proceedings of the 22nd ACM International Conference on Information and Knowledge Management, 2013

2012
A parallel and distributed meta-heuristic framework based on partially ordered knowledge sharing.
J. Parallel Distributed Comput., 2012

An ILP-based Worst-case Performance Analysis Technique for Distributed Real-time Embedded Systems.
Proceedings of the 33rd IEEE Real-Time Systems Symposium, 2012

A lifetime aware buffer assignment method for streaming applications on DRAM/PRAM hybrid memory (Extended abstract).
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

Executing synchronous dataflow graphs on a SPM-based multicore architecture.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Library Support in an Actor-Based Parallel Programming Platform.
IEEE Trans. Ind. Informatics, 2011

Fast, Energy Efficient Scan inside Flash Memory.
Proceedings of the International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures, 2011

Software synthesis in the ESL methodology for multicore embedded systems.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Resource minimized static mapping and dynamic scheduling of SDF graphs.
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
The Role of User Resistance in the Adoption of a Mobile Data Service.
Cyberpsychology Behav. Soc. Netw., 2010

Task-level timed-functional simulation for multi-core embedded systems.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

A task remapping technique for reliable multi-core embedded systems.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Decidable Signal Processing Dataflow Graphs: Synchronous and Cyclo-Static Dataflow Graphs.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Multiprocessor SoC design methods and tools.
IEEE Signal Process. Mag., 2009

2008
Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic Behavior.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2006
PBPAIR: an energy-efficient error-resilient encoding using probability based power aware intra refresh.
ACM SIGMOBILE Mob. Comput. Commun. Rev., 2006

Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Probability Based Power Aware Error Resilient Coding.
Proceedings of the 25th International Conference on Distributed Computing Systems Workshops (ICDCS 2005 Workshops), 2005

Shift buffering technique for automatic code synthesis from synchronous dataflow graphs.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs.
Proceedings of the 2005 International Conference on Compilers, 2005

2004
Fractional Rate Dataflow Model for Efficient Code Synthesis.
J. VLSI Signal Process., 2004

2003
Memory-Optimized Software Synthesis from Dataflow Program Graphs with Large Size Data Samples.
EURASIP J. Adv. Signal Process., 2003

2002
Fractional rate dataflow model and efficient code synthesis for multimedia applications.
Proceedings of the 2002 Joint Conference on Languages, 2002

Efficient code synthesis from extended dataflow graphs for multimedia applications.
Proceedings of the 39th Design Automation Conference, 2002

Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2000
Data memory minimization by sharing large size buffers.
Proceedings of ASP-DAC 2000, 2000

1999
A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1996
A Static Scheduling Heuristic for Heterogeneous Processors.
Proceedings of the Euro-Par '96 Parallel Processing, 1996


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