Hyunkyu Park

Orcid: 0000-0002-7226-6110

Affiliations:
  • Seoul National University, Department of Electrical and Computer Engineering, South Korea


According to our database1, Hyunkyu Park authored at least 7 papers between 2018 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces.
IEEE Access, 2022

2021
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer.
IEEE J. Solid State Circuits, 2021

A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface.
IEEE J. Solid State Circuits, 2021

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ Calibration for Memory Interfaces.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018


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