Hyunjoon Kim
Orcid: 0000-0001-9906-073X
According to our database1,
Hyunjoon Kim
authored at least 35 papers
between 2008 and 2024.
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Bibliography
2024
CoRR, 2024
Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout.
CoRR, 2024
Negative Sampling in Next-POI Recommendations: Observation, Approach, and Evaluation.
Proceedings of the ACM on Web Conference 2024, 2024
Proceedings of the 3rd ACM Workshop on the Security Implications of Deepfakes and Cheapfakes, 2024
2023
BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
Fast subgraph query processing and subgraph matching via static and dynamic equivalences.
VLDB J., March, 2023
Int. J. Prod. Res., February, 2023
BICE: Exploring Compact Search Space by Using Bipartite Matching and Cell-Wide Verification.
Proc. VLDB Endow., 2023
IEEE Access, 2023
DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 64 Kb Reconfigurable Full-Precision Digital ReRAM-Based Compute-In-Memory for Artificial Intelligence Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2022
CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2022
A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Hybrid dynamic programming with bounding algorithm for the multi-profit orienteering problem.
Eur. J. Oper. Res., 2022
Optimal sequence for single server scheduling incorporating a rate-modifying activity under job-dependent linear deterioration.
Eur. J. Oper. Res., 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks.
IEEE J. Solid State Circuits, 2021
Proceedings of the SIGMOD '21: International Conference on Management of Data, 2021
A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
31.2 CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Efficient Subgraph Matching: Harmonizing Dynamic Programming, Adaptive Matching Order, and Failing Set Together.
Proceedings of the 2019 International Conference on Management of Data, 2019
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks.
Proceedings of the 2019 International SoC Design Conference, 2019
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
2016
Theor. Comput. Sci., 2016
2008
Proceedings of the Fourth International Conference on Autonomic and Autonomous Systems, 2008