Hyungmin Cho
Orcid: 0000-0001-8705-7066
According to our database1,
Hyungmin Cho
authored at least 34 papers
between 2007 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
BiRD: Bi-Directional Input Reuse Dataflow for Enhancing Depthwise Convolution Performance on Systolic Arrays.
IEEE Trans. Computers, December, 2024
2023
FlexKA: A Flexible Karatsuba Multiplier Hardware Architecture for Variable-Sized Large Integers.
IEEE Access, 2023
2022
IEEE Trans. Parallel Distributed Syst., 2022
ES4D: Accelerating Exact Similarity Search for High-Dimensional Vectors via Vector Slicing and In-SSD Computation.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
RiSA: A Reinforced Systolic Array for Depthwise Convolutions and Embedded Tensor Reshaping.
ACM Trans. Embed. Comput. Syst., 2021
IEEE Access, 2021
IEEE Access, 2021
2019
GPU-based acceleration of the Linear Complexity Test for random number generator testing.
J. Parallel Distributed Comput., 2019
IEEE Access, 2019
Corrections to "Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects".
IEEE Access, 2019
Correction to "ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols".
IEEE Access, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
2018
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols.
IEEE Access, 2018
Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects.
IEEE Access, 2018
Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2016
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Eigenmode BER based MU-MIMO scheduling for rate maximization with linear precoding and power allocation.
Proceedings of the 2012 IEEE Wireless Communications and Networking Conference, 2012
Proceedings of IEEE International Conference on Communications, 2012
2011
2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
High recording density hard disk channel equalization using a bilinear recursive polynomial model.
IEICE Electron. Express, 2009
2007
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007