Hyungil Chae

According to our database, Hyungil Chae authored at least 17 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method.

Jonghyun Kim, Hyungil Chae

IEEE J. Solid State Circuits, July, 2024

A 150-MS/s, 65-dB SNDR Fully Passive Bandpass Noise-Shaping SAR ADC.

Dongsik Lee, Seungjun Lee, Hyungil Chae

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

A 50MHz-BW 168.8dB-FoM 2x Time-Interleaved Bandpass Noise Shaping SAR ADC Using Passive Filter.

Seungjun Song, Dongsik Lee, Hyungil Chae

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

A 600-MS/s, 65-dB SNDR, 75-MHz BW Time-Interleaved Noise-Shaping SAR ADC.

Jihyun Baek, Hyungil Chae

IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

A 3.68 aF_rms Resolution Continuous-Time Bandpass Δ Σ Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18 μm CMOS.

Sujin Park, Hyungil Chae, SeongHwan Cho

IEEE J. Solid State Circuits, 2023

2021

Readout Integrated Circuit for Small-Sized and Low-Power Gas Sensor Based on HEMT Device.

Seungjun Lee, Joohwan Jin, Jihyun Baek, Juyong Lee, Hyungil Chae

Sensors, 2021

An 85 dB DR 4 MHz BW Pipelined Noise-Shaping SAR ADC With 1-2 MASH Structure.

Sein Oh, Younggyun Oh, Juyong Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae

IEEE J. Solid State Circuits, 2021

A 74-dB Dynamic-Range 625-kHz Bandwidth Second-Order Noise-Shaping SAR ADC Utilizing a Temperature-Compensated Dynamic Amplifier and a Digital Mismatch Calibration.

Jae Sik Yoon, Jiyoon Hong, Hyungil Chae, Jintae Kim

IEEE Access, 2021

A 3.68aFrms Resolution 183dB FoMs 4^th-order Continuous-Time Bandpass ∆Σ Capacitance-to-Digital Converter in 0.18µm CMOS.

Sujin Park, Hyungil Chae, SeongHwan Cho

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020

Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC.

Juyoung Lee, Younggyun Oh, Sein Oh, Hyungil Chae

Sensors, 2020

A 80dB DR 6MHz Bandwidth Pipelined Noise-Shaping SAR ADC with 1-2 MASH structure.

Sein Oh, Younggyun Oh, Juyoung Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited).

Michael P. Flynn, Jaehun Jeong, Sunmin Jang, Hyungil Chae, Daniel Weyer, Rundao Lu, John Bell

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

4-Contact structure of vertical-type CMOS Hall device for 3-D magnetic sensor.

Sein Oh, Dong-young Hwang, Hyungil Chae

IEICE Electron. Express, 2019

2017

Double-sampling highpass delta-sigma modulator with inherent frequency translation.

Hyungil Chae

IEICE Electron. Express, 2017

2016

A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability.

Hyungil Chae, Michael P. Flynn

IEEE J. Solid State Circuits, 2016

2014

A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF.

Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn

IEEE J. Solid State Circuits, 2014

2012

A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF.

Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012