Hyung-Sik Won

According to our database, Hyung-Sik Won authored at least 2 papers between 2010 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

A 1.2V 23nm 6F² 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture.

Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2010

A bitline sense amplifier for offset compensation.

Myoung Jin Lee, Ki Myung Kyung, Hyung-Sik Won, Myoung Su Lee, Kun Woo Park

Proceedings of the IEEE International Solid-State Circuits Conference, 2010