Hyunchul Shin
Orcid: 0000-0003-3020-5130
According to our database1,
Hyunchul Shin
authored at least 60 papers
between 1986 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Infrared and visible image fusion using a feature attention guided perceptual generative adversarial network.
J. Ambient Intell. Humaniz. Comput., July, 2023
2022
Camera and LiDAR-based point painted voxel region-based convolutional neural network for robust 3D object detection.
J. Electronic Imaging, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Two-stream small-scale pedestrian detection network with feature aggregation for drone-view videos.
Multidimens. Syst. Signal Process., 2021
2020
Performance enhancement techniques for traffic sign recognition using a deep neural network.
Multim. Tools Appl., 2020
2019
IET Circuits Devices Syst., 2019
Context-aware pedestrian detection especially for small-sized instances with Deconvolution Integrated Faster RCNN (DIF R-CNN).
Appl. Intell., 2019
2018
New Dark Area Sensitive Tone Mapping for Deep Learning Based Traffic Sign Recognition.
Sensors, 2018
IET Image Process., 2018
IET Comput. Vis., 2018
Proceedings of the International SoC Design Conference, 2018
Infrared and Visible Image Fusion using Multi-Scale Decomposition and Visual Saliency Map.
Proceedings of the International SoC Design Conference, 2018
Proceedings of the International SoC Design Conference, 2018
2017
Charge-sharing read port with bitline pre-charging and sensing scheme for low-power SRAMs.
Int. J. Circuit Theory Appl., 2017
Robust hypothesis generation method using binary blob analysis for multi-lane detection.
IET Image Process., 2017
IET Comput. Vis., 2017
Effective regularity extraction and placement techniques for datapath-intensive circuits.
IET Circuits Devices Syst., 2017
Proceedings of the International SoC Design Conference, 2017
2016
J. Vis. Commun. Image Represent., 2016
IET Image Process., 2016
Road vanishing point detection using weber adaptive local filter and salient-block-wise weighted soft voting.
IET Comput. Vis., 2016
Proceedings of the Internet of Vehicles - Technologies and Services, 2016
2015
Real-time single image dehazing using block-to-pixel interpolation and adaptive dark channel prior.
IET Image Process., 2015
IET Comput. Vis., 2015
IEICE Electron. Express, 2015
2014
Control signal aware slice-level window based legalization method for FPGA placement (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the International Conference on Computer, 2014
Proceedings of the International Conference on Computer, 2014
2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Game theory-based resource allocation strategy for clustering based wireless sensor network.
Proceedings of the 6th International Conference on Ubiquitous Information Management and Communication, 2012
An Efficient Pedestrian Detection Method by Using Coarse-to-Fine Detection and Color Histogram Similarity.
Proceedings of the Convergence and Hybrid Information Technology, 2012
Proceedings of the Convergence and Hybrid Information Technology, 2012
2011
Proceedings of the Convergence and Hybrid Information Technology, 2011
2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2007
Operation Mode Based High-Level Switching Activity Analysis for Power Estimation of Digital Circuits.
IEICE Trans. Commun., 2007
IEICE Trans. Commun., 2007
2006
A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth.
IEEE Trans. Very Large Scale Integr. Syst., 2006
2003
A hardware-like high-level language based environment for 3D graphics architecture exploration.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
Proceedings of the 2001 ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, 2001
1999
1998
A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
1996
A performance-driven logic emulation system: FPGA network design and performance-driven partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
Performance-driven circuit partitioning for prototyping by using multiple FPGA chips.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1993
IEEE Trans. Very Large Scale Integr. Syst., 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
1992
Proceedings of the 29th Design Automation Conference, 1992
1990
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990
1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989
1987
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987
1986
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986