Hyun-Geun Byun
According to our database1,
Hyun-Geun Byun
authored at least 16 papers
between 2003 and 2008.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2008
A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation.
IEEE J. Solid State Circuits, 2007
2006
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
IEEE J. Solid State Circuits, 2005
IEICE Trans. Electron., 2005
A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Proceedings of the Systems Modeling and Simulation: Theory and Applications, 2004
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003