Hyuk-Jun Lee

Munhyung Lee

IEEE Access, 2023

2022

STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

2020

Multitoken-Based Power Management for NAND Flash Storage Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Per-Operation Reusability Based Allocation and Migration Policy for Hybrid Cache.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

EANeM: Energy-Aware Network Stack Management for Mobile Devices.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers.

[BibT_eX]

[DOI]

Dongkeon Choi

IEICE Trans. Electron., 2019

IP-aware cache partition and replacement scheme for mobile computing devices.

[BibT_eX]

[DOI]

Bobae Kim

IEICE Electron. Express, 2019

2018

Parameterised codebook design based on channel statistics for efficient multi-rank MIMO transmission.

[BibT_eX]

[DOI]

IET Commun., 2018

Energy Efficient Mobile Positioning System Using Adaptive Particle Filter.

[BibT_eX]

[DOI]

Yoojin Kim

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Application specific cache design using STT-RAM based block-RAM for FPGA-based soft processors.

[BibT_eX]

[DOI]

Hyunwoo Park

Hyun So

IEICE Electron. Express, 2018

A High-Bandwidth PCM-Based Memory System for Highly Available IP Routing Table Lookup.

[BibT_eX]

[DOI]

Chinam Kim

IEEE Comput. Archit. Lett., 2018

2017

Scalable Bandwidth Shaping Scheme via Adaptively Managed Parallel Heaps in Manycore-Based Network Processors.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

FeSSD: A Fast Encrypted SSD Employing On-Chip Access-Control Memory.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

2016

Implementation of a large-scale language model adaptation in a cloud environment.

[BibT_eX]

[DOI]

Multim. Tools Appl., 2016

2014

An Adaptive Idle-Time Exploiting Method for Low Latency NAND Flash-Based Storage Devices.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Classifying Useful Motion Vectors for Efficient Frame Rate Up Conversion of MC-DCT Encoded Video Streams.

[BibT_eX]

[DOI]

Jongho Nang

Sangchul Kim

J. Inf. Sci. Eng., 2014

Design of a bitmap-based QoS-aware memory controller for a packet memory.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

An optimal DRAM sizing and partitioning method for NVRAM based hybrid memory architecture.

[BibT_eX]

[DOI]

Jongbum Lim

IEICE Electron. Express, 2014

A dynamic block device reconfiguration algorithm in virtual MapReduce cluster.

[BibT_eX]

[DOI]

Clust. Comput., 2014

2013

A Performance and Usability Aware Secure Two-Factor User Authentication Scheme for Wireless Sensor Networks.

[BibT_eX]

[DOI]

Sang Guun Yoo

Juho Kim

Int. J. Distributed Sens. Networks, 2013

A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method.

[BibT_eX]

[DOI]

Seung-Chul Kim

IEICE Trans. Inf. Syst., 2013

Page overwriting method for performance improvement of NAND flash memories.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2013

Implementation of a Large-Scale Language Model in a Cloud Environment for Human-Robot Interaction.

[BibT_eX]

[DOI]

Proceedings of the Information Technology Convergence, 2013

2012

Analytical memory bandwidth model for many-core processor based systems.

[BibT_eX]

[DOI]

Woo-Cheol Cho

IEICE Electron. Express, 2012

2008

Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

2007

Latency-Aware Bus Arbitration for Real-Time Embedded Systems.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2007

Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis.

[BibT_eX]

[DOI]

Sung Woo Chung

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2000

Exploiting Parallelism and Data Locality of Systolic Array Applications using Multi-Ported FPGA.

[BibT_eX]

Albert A. Liddicoat

Michael J. Flynn

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Coarse-grained carry architecture for FPGA (poster abstract).

[BibT_eX]

[DOI]