Hyoukjun Kwon

Orcid: 0000-0001-9824-1352

According to our database1, Hyoukjun Kwon authored at least 38 papers between 2017 and 2024.

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Bibliography

2024
Optimized Spatial Architecture Mapping Flow for Transformer Accelerators.
CoRR, 2024

Characterizing the Accuracy - Efficiency Trade-off of Low-rank Decomposition in Language Models.
CoRR, 2024

PipeOrgan: Efficient Inter-operation Pipelining with Flexible Spatial Organization and Interconnects.
CoRR, 2024

SCAR: Scheduling Multi-Model AI Workloads on Heterogeneous Multi-Chiplet Module Accelerators.
CoRR, 2024

NonGEMM Bench: Understanding the Performance Horizon of the Latest ML Workloads with NonGEMM Workloads.
CoRR, 2024

2023
Inter-Layer Scheduling Space Exploration for Multi-model Inference on Heterogeneous Chiplets.
CoRR, 2023

XRBench: An Extended Reality (XR) Machine Learning Benchmark Suite for the Metaverse.
Proceedings of the Sixth Conference on Machine Learning and Systems, 2023

DREAM: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication.
IEEE Trans. Parallel Distributed Syst., 2022

Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators.
ACM Trans. Archit. Code Optim., 2022

A Formalism of DNN Accelerator Flexibility.
Proc. ACM Meas. Anal. Comput. Syst., 2022

SDRM3: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads.
CoRR, 2022

Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

2021
Flexion: A Quantitative Metric for Flexibility in DNN Accelerators.
IEEE Comput. Archit. Lett., 2021

Extending Sparse Tensor Accelerators to Support Multiple Compression Formats.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

Heterogeneous Dataflow Accelerators for Multi-DNN Workloads.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Data Orchestration in Deep Learning Accelerators
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01767-4, 2020

Data- and communication-centric approaches to model and design flexible deep neural network accelerators.
PhD thesis, 2020

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.
IEEE Trans. Very Large Scale Integr. Syst., 2020

MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings.
IEEE Micro, 2020

MARVEL: A Decoupled Model-driven Approach for Efficiently Mapping Convolutions on Spatial DNN Accelerators.
CoRR, 2020

SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
HERALD: Optimizing Heterogeneous DNN Accelerators for Edge Devices.
CoRR, 2019

Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Understanding the Impact of On-chip Communication on DNN Accelerator Performance.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A Communication-Centric Approach for Designing Flexible DNN Accelerators.
IEEE Micro, 2018

MAESTRO: An Open-source Infrastructure for Modeling Dataflows within Deep Learning Accelerators.
CoRR, 2018

Architecting a Secure Wireless Network-on-Chip.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Spoofing Prevention via RF Power Profiling in Wireless Network-on-Chip.
Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2018

MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Rethinking NoCs for Spatial Neural Network Accelerators.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Adaptive Manycore Architectures for Big Data Computing.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Proving Flow Security of Sequential Logic via Automatically-Synthesized Relational Invariants.
Proceedings of the 30th IEEE Computer Security Foundations Symposium, 2017


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