Hyojin Choi

According to our database, Hyojin Choi authored at least 12 papers between 2007 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Learning Gate-level Netlist Testability in the Presence of Unknowns through Graph Neural Networks.

Thai-Hoang Nguyen, Youngjin Ju, Dongsub Yoon, Hyojin Choi

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2021

Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs.

Hyojin Choi, In Huh, Seungju Kim, Jeonghoon Ko, Changwook Jeong, Hyeonsik Son, Kiwon Kwon, Joonwan Chai, Younsik Park, Jaehoon Jeong, Daesin Kim, Jung Yun Choi

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2015

Demo: Human-Interactive Hardware-In-the-Loop Simulator for Cooperative Intelligent Transportation Systems and services.

Seokil Song, Taein Jeon, Eungjin Kim, Jinsu Kim, Dojin Choi, Yeona Kim, Hyojin Choi, Kyunbyoung Ko, Cheol Mun

Proceedings of the 2015 IEEE Vehicular Networking Conference, 2015

Poster: Development of ICA algorithm for V2X communications by using PreScan.

Min Baek, Hwan Lee, Hyojin Choi, Kyunbyoung Ko

Proceedings of the 2015 IEEE Vehicular Networking Conference, 2015

2012

A simulation-based study for DRAM power reduction strategies in GPGPUs.

Hyojin Choi, Kyuyeon Hwang, Jae-Woo Ahn, Wonyong Sung

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Performance analysis of multi-bank DRAM with increased clock frequency.

Su-Jin Cho, Jae-Woo Ahn, Hyojin Choi, Wonyong Sung

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Reducing off-chip memory traffic by selective cache management scheme in GPGPUs.

Hyojin Choi, Jae-Woo Ahn, Wonyong Sung

Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units, 2012

2011

Memory access pattern-aware DRAM performance model for multi-core systems.

Hyojin Choi, Jongbok Lee, Wonyong Sung

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

2010

VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory.

Hyojin Choi, Wei Liu, Wonyong Sung

IEEE Trans. Very Large Scale Integr. Syst., 2010

2008

Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP.

Wonchul Lee, Hyojin Choi, Wonyong Sung

J. Signal Process. Syst., 2008

2007

Fast Block Mode Decision for H.264/AVC on a Programmable Digital Signal Processor.

Wonchul Lee, Hyojin Choi, Wonyong Sung

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding.

Hyojin Choi, Wonchul Lee, Wonyong Sung

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007