Hyman Shanan
According to our database1,
Hyman Shanan
authored at least 8 papers
between 2004 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2022
A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2019
An Eight-Phase 40GHz RTWO in 28nm CMOS with Phase Noise Reduction Via Head and Tail Filtering.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2014
0.3-4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital Δ-Σ Modulator-Based Divider Controller.
IEEE J. Solid State Circuits, 2014
2013
High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators.
Proceedings of the ESSCIRC 2013, 2013
2009
IEEE Commun. Mag., 2009
A 2.4GHz 2Mb/s versatile PLL-based transmitter using digital pre-emphasis and auto calibration in 0.18µm CMOS for WPAN.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A highly integrated low-power 2.4GHz transceiver using a direct-conversion diversity receiver in 0.18µm CMOS for IEEE802.15.4 WPAN.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2004
A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004