Hyeseung Jang
According to our database1,
Hyeseung Jang
authored at least 2 papers
in 2022.
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Bibliography
2022
Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs.
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes.
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022