Hyeonuk Kim
Orcid: 0000-0001-7719-8172
According to our database1,
Hyeonuk Kim
authored at least 12 papers
between 2016 and 2024.
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Bibliography
2024
ADC-Free ReRAM-Based In-Situ Accelerator for Energy-Efficient Binary Neural Networks.
IEEE Trans. Computers, February, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
S-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level Sparsity.
IEEE Trans. Computers, 2022
2021
Candidate point selection using a self-attention mechanism for generating a smooth volatility surface under the SABR model.
Expert Syst. Appl., 2021
2020
An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices.
IEEE J. Solid State Circuits, 2020
2019
J. Comput. Phys., 2019
Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
An integral equation representation approach for valuing Russian options with a finite time horizon.
Commun. Nonlinear Sci. Numer. Simul., 2016