Hyeonjun Cheon

According to our database, Hyeonjun Cheon authored at least 3 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of six.

2025

URcon: Unified and Reconfigurable Control and Verification Platform for Multi-Mode Customized eDRAM and SRAM Macros.

Ho-Sung Lee, Ik-Hyeon Jeon, Jiwon Lee, Hyeonjun Cheon, Joo-Hyung Chae

IEEE Access, 2025

2024

Design of 16-Kb 6T SRAM Supporting Wide Parallel Data Access for Enhanced Computation Speed.

Jiwon Lee, Hyeonjun Cheon, Ho-Sung Lee, Ik-Hyeon Jeon, Joo-Hyung Chae

Proceedings of the 21st International SoC Design Conference, 2024

A 16-Kb 1T1C DRAM Supporting Conventional and Compute-in-Memory Access Modes.

Hyeonjun Cheon, Ho-Sung Lee, Jiwon Lee, Ik-Hyeon Jeon, Joo-Hyung Chae

Proceedings of the 21st International SoC Design Conference, 2024