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Hyeonho Han

Orcid: 0009-0006-2028-9130

According to our database1, Hyeonho Han authored at least 3 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A Highly Digital 143.2-dB DR Sub-1° Phase Error Impedance Monitoring IC With Pulsewidth Modulation Frontend.
[BibTeX]
[DOI]
Hyeonho Han
,
Byungchoul Park
,
Jaesuk Sung
,
Heonjin Choi
,
Youngcheol Chae
IEEE J. Solid State Circuits, April, 2024

2023
A Highly-Digital PWM-Based Impedance Monitoring IC with 143.2dB DR and 17.7fFrms Resolution.
[BibTeX]
[DOI]
Hyeonho Han
,
Woojun Choi
,
Jaehyun Kim
,
Jaesuk Sung
,
Heonjin Choi
,
Youngcheol Chae
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2019
A 0.02mm<sup>2</sup> 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture.
[BibTeX]
[DOI]
Hyeonho Han
,
Woojun Choi
,
Youngcheol Chae
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019


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