Hyeongyeol Park

According to our database, Hyeongyeol Park authored at least 2 papers between 2014 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2021

A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.

Kyunghoon Kim, Joo-Hyung Chae, Jaehyeok Yang, Jihyo Kang, Gang-Sik Lee, Sang-Yeon Byeon, Youngtaek Kim, Boram Kim, Dong-Hyun Kim, Yeongmuk Cho, Kangmoo Choi, Hyeongyeol Park, Junghwan Ji, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Kyubong Kong, Sunho Kim, Sangkwon Lee, Junhyun Chun, Hyungsoo Kim, Seon-Yong Cha

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2014

A 3.8 MHz CMOS Wien-bridge oscillator with differential capacitive automatic amplitude control.

Hyeongyeol Park, Hyunchol Shin

IEICE Electron. Express, 2014