Hyeon Uk Sim

According to our database1, Hyeon Uk Sim authored at least 16 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2022
MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Non-uniform Step Size Quantization for Accurate Post-training Quantization.
Proceedings of the Computer Vision - ECCV 2022, 2022

2021
Automated Log-Scale Quantization for Low-Cost Deep Neural Networks.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

2020
SparTANN: sparse training accelerator for neural networks with threshold-based sparsification.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

2019
Cost-effective stochastic MAC circuits for deep neural networks.
Neural Networks, 2019

Successive Log Quantization for Cost-Efficient Neural Networks Using Stochastic Computing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Log-quantized stochastic computing for memory and computation efficient DNNs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Sign-magnitude SC: getting 10X accuracy for free in stochastic computing for deep neural networks.
Proceedings of the 55th Annual Design Automation Conference, 2018

DPS: dynamic precision scaling for stochastic computing-based deep neural networks.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
FPGA implementation of convolutional neural network based on stochastic computing.
Proceedings of the International Conference on Field Programmable Technology, 2017

A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

Scalable stochastic-computing accelerator for convolutional neural networks.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2014
Flattening-based mapping of imperfect loop nests for CGRAs?
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014


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