Hyeon-June Kim
Orcid: 0000-0002-0516-5811
According to our database1,
Hyeon-June Kim
authored at least 17 papers
between 2014 and 2024.
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Bibliography
2024
An Analog Adaptive Reference Generation Readout Integrated Circuit for Baseline-Free Gas Sensor Measurements.
IEEE Trans. Instrum. Meas., 2024
An Intrascene Wide Dynamic Range CMOS Image Sensor Using Dual-Gain Ramp Generator for Machine Vision Applications.
IEEE Trans. Instrum. Meas., 2024
Development and validation of a 64-channel ROIC prototype for SWIR line scan sensor applications.
Integr., 2024
Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications.
Integr., 2024
High Dynamic Range Object Detection System with Image Fusion Network Using High-Illumination Specialized Binary Image.
Proceedings of the 2024 IEEE SENSORS, Kobe, Japan, October 20-23, 2024, 2024
2023
Theoretical and Experimental Analysis of Reversed Uneven Power Splitting Technique in GaN MMIC Doherty Power Amplifiers.
IEEE Access, 2023
A Chemoresistive Gas Sensor Readout Integrated Circuit With Sensor Offset Cancellation Technique.
IEEE Access, 2023
2022
Chemoresistive Sensor Readout Circuit Design for Detecting Gases with Slow Response Time Characteristics.
Sensors, 2022
2021
11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors.
IEEE J. Solid State Circuits, 2021
IEICE Electron. Express, 2021
2019
A High-Multi Target Resolution Focal Plane Array-Based Laser Detection and Ranging Sensor.
Sensors, 2019
2017
IEEE J. Solid State Circuits, 2017
2016
A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs.
IEEE J. Solid State Circuits, 2016
2015
A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory.
IEEE J. Solid State Circuits, 2015
Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014