Hyemun Lee
According to our database1,
Hyemun Lee
authored at least 2 papers
between 2023 and 2024.
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Bibliography
2024
13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023