Hye-Seung Yu

According to our database¹, Hye-Seung Yu authored at least 6 papers between 2005 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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PhD thesis

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Bibliography

2023

A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021

Industry's First 7.2 Gbps 512GB DDR5 Module.

[BibT_eX]

[DOI]

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2017

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

2016

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2005

An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Hye-Seung Yu

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