Hye-Jung Kwon
According to our database1,
Hye-Jung Kwon
authored at least 9 papers
between 2011 and 2023.
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Bibliography
2023
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ.
IEEE J. Solid State Circuits, 2023
2022
A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
2019
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
IEEE J. Solid State Circuits, 2019
2018
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2014
Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 0.4 V driving multi-touch capacitive sensor with the driving signal frequency set to (n+0.5) times the inverse of the LCD VCOM noise period.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2011
A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011