Hwang-Cherng Chow

According to our database, Hwang-Cherng Chow authored at least 19 papers between 1992 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Complex Human Activities Recognition Based on High Performance 1D CNN Model.

Raman Maurya, Tee Hui Teo, Shi Hui Chua, Hwang-Cherng Chow, I-Chyn Wey

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

2017

A Simple Drain Current Model for MOS Transistors with the Lorentz Force Effect.

Hwang-Cherng Chow, Prasenjit Chatterjee, Wu-Shiung Feng

Sensors, 2017

2016

Drain Current Modulation of a Single Drain MOSFET by Lorentz Force for Magnetic Sensing Application.

Prasenjit Chatterjee, Hwang-Cherng Chow, Wu-Shiung Feng

Sensors, 2016

2014

Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuits.

I-Chyn Wey, Chien-Chang Peng, Hwang-Cherng Chow

Int. J. Circuit Theory Appl., 2014

2008

A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications.

Hwang-Cherng Chow, Pu-Nan Weng

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A high performance peak detector sample and hold circuit for detecting power supply noise.

Hwang-Cherng Chow, Zhi-Hau Hor

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

High CMRR instrumentation amplifier for biomedical applications.

Hwang-Cherng Chow, Jia-Yu Wang

Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007

1V 10-bit successive approximation ADC for low power biomedical applications.

Hwang-Cherng Chow, Yi-Hung Chen

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2005

A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications.

Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

High performance sense amplifier circuit for low power SRAM applications.

Hwang-Cherng Chow, Shu-Hsien Chang

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder.

Hwang-Cherng Chow, I-Chyn Wey

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

A 3.3 V 1 GHz high speed pipelined Booth multiplier.

Hwang-Cherng Chow, I-Chyn Wey

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

New pixel-shared design and split-path readout of CMOS image sensor circuits.

Hwang-Cherng Chow, Yung-Kuo Ho

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

High performance automatic gain control circuit using a S/H peak-detector for ASK receiver.

Hwang-Cherng Chow, I-Hsin Wang

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2000

Novel output buffer designs for universal serial bus IC applications.

Hwang-Cherng Chow, Chen-Yi Huang, Chih-Hong Chang

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999

Bidirectional buffer for mixed voltage applications.

Hwang-Cherng Chow

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Duty cycle control circuit and applications to frequency dividers.

Hwang-Cherng Chow

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1992

An analytical CMOS inverter delay model including channel-length modulations.

Hwang-Cherng Chow, Wu-Shiung Feng

IEEE J. Solid State Circuits, September, 1992

An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation.

Hwang-Cherng Chow, Wu-Shiung Feng, James B. Kuo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992