Hwan-Wook Park
According to our database1,
Hwan-Wook Park
authored at least 4 papers
between 2006 and 2010.
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Bibliography
2010
A 31 ns Random Cycle VCAT-Based 4F <sup>2</sup> DRAM With Manufacturability and Enhanced Cell Efficiency.
IEEE J. Solid State Circuits, 2010
2009
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.
IEEE J. Solid State Circuits, 2009
2007
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits, 2007
2006
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006