Hwa-Chyi Chiou

According to our database, Hwa-Chyi Chiou authored at least 2 papers between 2015 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances.

Shao-Chang Huang, Chih-Cherng Liao, Hsien-Feng Liao, Shou-Peng Weng, Karuna Nidhi, Yu-Kai Wang, Yi-Jen Chen, Hwa-Chyi Chiou, Yeh-Ning Jou, Jian-Hsing Lee

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

2015

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection.

Seian-Feng Liao, Kai-Neng Tang, Ming-Dou Ker, Jia-Rong Yeh, Hwa-Chyi Chiou, Yeh-Jen Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin

Proceedings of the European Conference on Circuit Theory and Design, 2015